Implementation of a $2\times 2$ MIMO-OFDM receiver on an application specific processor

Abstract

This paper describes the implementation of the hard computational kernels required for the baseband (BB) processing of a $2\times 2$ multiple-input multiple-output (MIMO)-OFDM receiver on a design-framework for application specific processors. The employed low-complexity BB algorithms are described and their computational complexity is derived. The receiver is split into two parts which are mapped onto two application specific processors, each tailored to the computational needs of the associated digital signal processing kernels. The first processor performs the per stream MIMO-OFDM processing. The second processor handles the MIMO detection. Finally, the $0.18\mathrm{\mu }\mathrm{m}$ 1P/6M CMOS technology layout of both fabricated application specific processors is presented. Real-time BB processing is possible on these engines running at a clock frequency of 250 MHz.

Introduction

The world of wireless communications is governed by a plethora of different standards, each tailored to the needs of its own target application domain (e.g., wireless local area network (WLAN) or cellular networks). Consequently, many standards employ different coding and modulation schemes. This heterogeneous, fast evolving environment is the motivation for the development of software defined radio (SDR) concepts. Ideally, SDRs are capable of handling all possible transmission techniques on the same platform, without the need of integrating dedicated modems for each standard.

Multiple-input multiple-output (MIMO) transmission is a recent development in the area of wireless communications that permits to increase the spectral efficiency by employing multiple antennas at both the transmitter and the receiver. Since its conception, MIMO communication has reached a level of maturity that permits integration of the technology into wireless communication standards. Examples of standards that already employ MIMO are the IEEE 802.11n standard for local area networks, the IEEE 802.16e standard for metropolitan area networks, or the 3GPP LTE standard for cellular systems.

Unfortunately, the tremendous computational complexity associated with MIMO signal processing at the receiver conflicts with the reduced amount of processing resources available in a low-cost software programmable architecture of an SDR solution. Hence, it appears reasonable to step back from the ambition of directly implementing the ultimate SDR transceiver that is capable of handling all present and future standards. The more pragmatic approach considered in this paper employs two levels of configurability: the first level is the use of an application specific processor design-framework which permits design-time customization to meet the requirements of a specific standard, thus enabling the rapid development of new products. The second level provides limited flexibility for reconfiguration at run-time. It enables bug-fixes, the incorporation of small changes to a standard, and upgrades to improved receiver algorithms.

A summary of the challenges associated with implementing fourth generation (4G) wireless communication systems on SDR architectures can be found in [1]. The authors conclude that technology scaling alone does not suffice to meet the stringent performance requirements of 4G systems. Hence, new architectural solutions are required. Two emerging approaches are investigated in [2]. The first approach comprises reconfigurable architectures with different levels of granularity. It is argued that success stories of companies that have followed this approach for mobile phones are still missing. The second approach follows a DSP-centric, accelerator assisted architecture. It is argued that this approach is more promising for the mobile phone market compared to the reconfigurable approach.

More specifically, concerning the application area under consideration in this paper, the potential of using reconfigurable hardware to support different systems which employ the same modulation techniques has been explored in [3] for the OFDM-based IEEE 802.11a and HIPERLAN/2 standards. In [4] the implementation of a minimal MIMO-OFDM receiver on the RaPiD coarse-grained reconfigurable architecture is considered. It is found that there is a sixfold increase in complexity compared to an ASIC implementation, while the cost is reduced by a factor of six compared to an implementation on conventional digital signal processors. A complete IEEE 802.11a baseband (BB) implementation on an application specific processor is presented in our previous work [5]. The implementation revealed that a standard-specific software programmable approach is feasible with only minor area overhead when compared to dedicated ASIC solutions. This encouraging result motivates the choice of the application specific processor design-framework for implementing the $2\times 2$ MIMO-OFDM receiver considered in this paper. While all of the above-described architectures consider cellular systems, single-antenna systems, or a minimal MIMO-OFDM receiver, a first implementation of a $2\times 2$ MIMO-OFDM WLAN receiver on the ADRES coarse grained array has been described in [6] and was further elaborated on in [7], [8].

In this paper, we consider the use of an application specific processor for implementing the BB processing of a $2\times 2$ MIMO-OFDM receiver. Our main contributions are the description of the application specific processor architecture and the description of the mapping of the MIMO-OFDM signal processing onto that architecture. We also provide a summary of the required algorithms together with an analysis of their computational complexity. Finally, our implementation results provide reference for the true silicon complexity of a real-time capable $2\times 2$ MIMO-OFDM receiver implemented on a software-programmable, i.e., reconfigurable hardware.

The remainder of this paper is structured as follows: Section 2 considers the algorithms required for the BB processing in a typical MIMO-OFDM receiver. It identifies the involved atomic operations, and analyzes the corresponding processing requirements for the general case and for the $2\times 2$ configuration under consideration in this paper. This analysis sets the stage for the subsequent discussion of our SDR implementation. We start with the introduction of the proposed application specific processor design-framework in Section 3. Section 4 describes a processor composition that is suitable for implementing a $2\times 2$ MIMO-OFDM receiver supporting a bandwidth of 20 MHz. It provides the relevant details of the corresponding run-time datapath configurations, the program flow, and the schedule. Section 5 summarizes our implementation results and compares the proposed solution to other works in the field. Conclusions are drawn in Section 6.