Performance improvement of commercial ISFET sensors using reactive ion etching

Highlights

• Successful one step RIE plasma etching for post-process CMOS ISFETs improvement.

• pH sensitivity - passivation capacitance increased by 125%–5700%, respectively.

• Capacitive attenuation is reduced by 96%.

Abstract

Reactive Ion Etching (RIE) is used to improve the performance of commercial Complementary Metal Oxide Semiconductor (CMOS) Ion-Sensitive Field-Effect Transistors (ISFETs) by thinning the top passivation layers inherent of the CMOS fabrication process. Using a combination of O2 and SF6 in 50% ratio, both polyimide and Si3N4 layers are etched in one etching step. Etching for different times we find the right remaining layer thickness for best ISFET performance to be ∼1 μm of SiO2. The results show an increase in pH sensitivity of 125%, a 5700% increase in passivation capacitance and a 96% reduction in capacitive attenuation. The RIE etch recipe can be used on multi-project wafers (MPW) to boost CMOS sensor performance.

Introduction

Complementary Metal Oxide Semiconductor (CMOS) technology has enabled the development of scalable and cheap integrated sensors for biomedical applications. Sensors such as the Ion-Sensitive Field-Effect Transistor (ISFET), used for pH sensing and analysis of various biomolecules such as proteins, enzymes and DNA [1], can be commercialised and integrated in the CMOS process with the extended gate approach [2,3]. This method introduces a passivation layer which, for a typical 0.35 μm process, consists of 1 μm Si3N4 and 1 μm SiO2 which are pH sensitive. Thus, large scale integration of ISFETs in CMOS is possible, enabling the development of novel devices and systems [4].

However, in multi-project wafers (MPW) the final top layer imposed by the CMOS process may be unknown. In the case of CMOS ISFET the top passivation layers are crucial for its functionality and can introduce attenuation of the reference voltage on the floating gate and degrade its sensitivity to pH below the ideal Nernstian of 59 mV/pH [2,3].

The ISFETs were designed in Cadence Virtuoso [5] using the extended gate approach with MOSFET gate oxide thickness 7.6 nm, width 5 μm and length 1 μm. The sensing area is defined by the top metal of 30 μm by 30 μm. The CMOS ISFET chips were fabricated in a commercial 0.35 μm CMOS process. An additional 4 μm thick polyimide layer is typically added during fabrication to release the stress on the materials and to ensure passivation remains intact, since the process has a thick top metal (thicker than the passivation), and it is easier for the passivation to crack. This polyimide layer is not pH sensitive and inhibits the ISFET operation significantly. The final structure and macromodel of the ISFET is shown in Fig. 1, where E_ref is the voltage established between the reference electrode and the solution, V_chem is a group of chemically related voltages in the electrolyte solution, V_tc is the voltage referred trapped charge [6], C_gouy and C_helm are the Gouy-Chapman and Helmholtz capacitances of the electrical double layer (EDL) respectively [7] and C_pass is the passivation capacitance [3,8].

We aim to restore pH sensitivity of CMOS ISFET sensors by post-processing using Reactive Ion Etching (RIE) to controllably remove CMOS process-imposed insulation layers and determine the optimum remaining SiO₂ layer thickness for sensing.