Research paperImpact of surface preparation for n-type Si:P and p-type SiGe:B semiconductors on low resistance silicide contacts
Graphical abstract
Introduction
With the continued scaling of logic technologies, has come the ever-more demanding need for low resistivity contacts in metal-oxide-semiconductor field effect transistors (MOSFETs). Serving as the coupling of the metal interconnect to the Source/Drain (S/D) regions of the semiconductor device, metal silicides have long been established as the dominant material to decrease parasitic resistance [1]. Previous work has focused on optimizing silicide formation conditions and so-called “interfacial engineering”, where local dopant concentrations and activation conditions can lead to a lower Schottky barrier and a more favorable contact [2], [3], [4], [5]. Due to the sensitivity of the contact to this interfacial composition, it follows that the preparation (removal of resistive oxides) and passivation (minimizing unbonded Si/Ge atoms) of the S/D semiconductor surface is crucial for achieving low contact resistivity.
Removal of post etch residue (PER) is necessary in order to achieve clean semiconductor surfaces, improving yield and proper function of devices. It is estimated that over 50% of the yield loss in semiconductor manufacturing is due to micro-contamination [6]. Hence, subsequent wet cleaning steps are necessary to remove residues from the bottom and sidewalls in high aspect ratio (HAR) contact features while maintaining targeted trench critical dimensions (CD). This requires minimizing lateral etch without damaging other exposed materials, such as etch-stop layers (ESL), with aqueous cleaning solutions. Typically, dilute hydrofluoric acid (dHF) solutions have been used to remove post etch residues [7], [8]. However, controlling the CD of a contact via for sub-10 nm nodes is stringent and meeting these targets is extremely challenging [9]. Recent publications demonstrate that ultra-dilute HF solutions (< 0.05 wt%), in the presence of additives and at an elevated temperature, give excellent control of targeted CD for ultra-low k films (k = 2.7) [10]. This approach for PER removal provides a pathway to evaluate an ultra-dilute modified HF solution for S/D contact cleaning.
In common integration schemes, an etch-stop layer is used to protect semiconductor surfaces from oxygen and fluorine-based reactive ion etch (RIE) chemistries during the dielectric etch. However, a challenge remains for a highly selective and directional removal of ESL films without attacking the underlying S/D semiconductor surface. One method to achieve low-damage is the use of a gas-cluster ion beam (GCIB) [11], [12], [13]. A wide variety of GCIB applications in semiconductor processing (e.g. low energy implant, controlled etching, planarization, thin film deposition) can be found in literature [14], [15]. In a recent publication, controlled Cu etching at room temperature (RT) and high vacuum conditions was achieved by controlled oxidation of Cu surface using O2-GCIB followed by the introduction of vapor acetic acid [12]. Acetic acid facilitated the CuO etching and the organic by-products formed during reaction were desorbed due to local and transient GCIB heating. These results indicate that the GCIB process can be highly effective in controlled etching of metal surfaces. However, O2-containing GCIB processes are not suitable for exposed SiGe:B/Si:P surfaces prior to metallization in S/D contact applications. Therefore, determining the impact of non-oxidizing reactive gases on semiconductor surfaces is necessary in deciding its viability in logic technologies.
In order to achieve atomically clean semiconductor surfaces for low contact resistance, any damaged or amorphous surfaces formed as a result of GCIB processing must be removed. Previous efforts to remove these highly resistive layers, coincidently reducing Schottky barrier height for carrier conduction, have included traditional aqueous solutions [16], hydrogen plasmas [17], and gaseous chemical etching [18]. Few comprehensive studies exist that present extensive materials/chemical characterization of these initial damaging processes paired with possible surface treatments' and their impact on electrical performance. In this work, we evaluate the contact resistivity impact of GCIB and the effectiveness of two aqueous cleaning solutions, alkaline and hydrofluoric acid (HF)-based, to remove GCIB-derived residues. The removal of PER and SiGe:B/Si:P damage was characterized by using XPS to study the evolution of the elemental composition and bonding states of the surface. Transmission electron microscopy was used to directly compare structural impacts in high aspect ratio contact trenches. Finally, an optimized cleaning sequence was electrically tested via a transmission line model to determine changes in specific contact resistivity.
Section snippets
Materials and methods
Epitaxial substrates Si:P and Si1 − xGex:B (x = 0.47) were grown on 300 mm wafers for fundamental characterization studies utilizing XPS. To simulate an integrated process flow, a thin silicon nitride (SiNx) film of ~ 5 nm was deposited as an ESL and subsequently removed via NF3 gas-cluster ion beam (GCIB) process. Two different wet chemical systems, an alkaline high pH (> 10) solution and a HF-based acidic solution, were then evaluated as possible beneficial surface treatments prior to metal
Effect of GCIB treatment on Si:P and Si0.63Ge0.47:B substrates
Surface composition of epitaxial surfaces as-grown and post-GCIB exposure was initially evaluated to determine incoming oxide composition before aqueous treatments. Fig. 1 shows the high resolution XPS spectra for Si 2p and Ge 3d for the native oxide film and post GCIB exposed surfaces for Si:P and Si0.53Ge0.47:B films. Deconvolution of the as-grown Si:P film shows all four oxidation states at binding energies of 100.5 eV (Si+ 1), 101.1 eV (Si+ 2), 101.9 eV (Si+ 3) and 103.2 eV (SiO2) with respect to
Conclusions
In summary, it was shown that etch chemistries such as GCIB can damage S/D semiconductor surfaces and impact contact resistivity in logic devices. The impact of aqueous treatments on surface composition was explored and demonstrated to improve the contact resistivity via electrical characterization. With this notable improvement, utilizing similar S/D surface treatments is seen as an important element for being able to meet contact resistivity requirements for future logic technology nodes.
Acknowledgements
This work was performed by the Alliance Teams at various IBM and Globalfoundries Research and Development Facilities.
References (28)
- et al.
Study of interaction between silicon surfaces in dilute ammonia peroxide mixtures (APM) and their components using atomic force microscope (AFM)
Microelectron. Eng.
(2011) - et al.
Impact of HF-based cleaning solutions on via resistance for sub-10 nm BEOL structures
Microelectron. Eng.
(2016) - et al.
Gas cluster ion beam infusion processing of semiconductors
Nucl. Inst. Methods Phys. Res. B
(2006) - et al.
Advancement of gas cluster ion beam processes for chemically enhanced surface modification and etching
Phys. Procedia
(2015) - et al.
Materials processing by gas cluster ion beams
Mater. Sci. Eng., R
(2001) - et al.
The chemical composition changes of silicon and phosphorus in the process of native oxide formation of heavily phosphorus doped silicon
Appl. Surf. Sci.
(2001) - et al.
Non-linear processes in the gas cluster ion beam modification of solid surfaces
Mater. Sci. Eng.
(1998) - et al.
High resolution XPS study of oxide layers grown on Ge substrates
Surf. Sci.
(2003) - et al.
Oxidation of Ge (100) and Ge (111) surfaces: an UPS and XPS study
Surf. Sci.
(1995) - et al.
The effects of contact size and non-zero metal resistance on the determination of specific contact resistance
Solid State Electron.
(1982)