Reliability enhancements of chip-on-chip package with layout designs of microbumps
Graphical abstract
Introduction
Three-dimensional (3D) integrated circuit (IC) packaging has been given much attention because it possesses several advantages over the traditional packaging technology, such as its high interconnect density, superior form factor, the integration of heterogeneous functions, and desirable performance [1]. Multi-chip stacking with a thinning procedure is generally implemented using simultaneous Cu–Cu or Cu–Sn thermocompression and adhesive buffer layer bonding [2]. However, this approach is still at the infancy stage and must be further developed to meet the reliability requirements and corresponding yields of the microelectronic industry. Consequently, the promising flip chip bonding process combined with the architecture of through-silicon via (TSV) is widely utilized in chip-to-chip interconnects of 3D integrations [3], [4]. Meanwhile, numerous critical reliability issues regarding the effects of TSVs and microbumps on thermal dissipation [5], joule heating, electromigration, stress-migration, cracking failure, and the structural warping of a stacked chips assembly [6], [7] have become severely challenging and require urgent resolution [8]. The energy-partitioning and Coffin–Manson approaches integrated with the finite element analysis (FEA) are suggested to estimate the thermomechanical reliability of microbumps using the mean failure time of microjoints and TSVs, respectively [9]. The mechanical properties of filled underfill and bump height are the most dominant factors that influence the reliability of 3D-IC packaging with stacked four chips. The locations of microbump-adjacent chips with a high magnitude of inelastic strain have become a particular concern caused by the large coefficient of thermal expansion (CTE) that occurs at this condition. Without the underfill, the measured shear strengths of bonded chips and microbumps exceed the demand specifications [10]. Compared with the dimensional orders of flip chip solder bumps, the microbumps dramatically decrease, which significantly induces the Ag3Sn production of intermetallic compounds (IMCs) as Pb-free SnAg solders are adopted. Interfacial cracks may be initiated and could grow at the locations of IMCs because 3D-IC packaging is subject to external stress [11]. To change the thermal stress distribution of bonding interface of microbumps and increase crack resistance, several Cu pillar bump types were examined by FEA [12]. The optimization of microbump layouts could be further performed to enhance the reliability of analytic 3D-IC packaging structures [13].
A review of the literature revealed that the use of underfill is necessary to improve the lifetime of microbumps. Consequently, a wafer-level underfill (WLUF) technique was presented to overcome the drawbacks of capillary actions used in the traditional underfill processes for a narrow bump gap [14], [15]. However, the issue of warping during the WLUF process influences the subsequent assembly of chip stacking and the mechanical reliability of microbumps. To investigate this concern, a vehicle for the chip-on-chip packaging structure (Fig. 1) is utilized to understand the warping induced by chip stacking. Using four microbump arrays combined with the WLUF process, a 5.1 mm × 5.1 mm top chip is assembled onto a 16 mm × 16 mm bottom chip. The detailed sizes of microbumps with a fine pitch of 30 μm are likewise revealed in Fig. 1(b). The cross-sectional views of microbumps under different magnitudes of bonding forces are shown in Fig. 2. The gap reduction between chips at the edge is extremely serious, as compared with the packaging center. To estimate the warping in the WLUF assembly and the mechanical reliability of a critical microbump during a temperature cycling period, a nonlinear simulation method is proposed in this study; the method is based on FEA integrated with process-oriented considerations. Furthermore, to address the issue of warping, two different layout designs for microbumps with dummy joints are systematically analyzed. These structural designs ensure the mechanical reliability of a WLUF technique.
Section snippets
Theory of thermal stress
The major driving force of structural failure caused by thermal stress has been a long-term concern for electronic devices. This observation is particularly true because thermal stress has an important influence on the reliability of 3D-IC packages. The sources of thermal stress could be grouped into two: (1) a temperature gradient distributed around a single material such as the operated condition of a silicon chip; and (2) the assembly of materials at the bonding interface with different
Process oriented stress simulation methodology
According to the dimensions revealed in Fig. 1, Fig. 3, a condition of geometrical symmetry is constructed to perform nonlinear process-oriented FEA after the thermocompression approach of WLUF. This symmetry is located along the cutting line of A′–A′ (Fig. 1), with half of a two-dimensional chip-on-chip packaging structure based on the assumption of plane strain. A total of 67 microbumps with a pitch of 30 μm in this FEA model is observed. Given that the broad region outside the microbump
Material property effects of WLUF on the Cu/Ni/SnAg microbump assembly
The material properties of traditional underfills used in flip chip technology having low-k chips are dominant factors that determine the failure mode of the whole packaging structure and their related long-term mechanical reliability. By contrast, the WLUF material consists of epoxy resin, fluxing agent, and silica particles at a high percentage of filler content. The WLUF is tack free and exhibits excellent dicing behaviors without delamination, dust, and cracking. Although the significant
Design effects of dummy microbumps on the assembly of chip-on-chip packaging
To retard warping or to sustain co-planarity during the assembly of chip-on-chip packages, as well as to enhance the mechanical reliability of critical microbumps under thermal cycling tests, a promising approach is to utilize the design concepts of dummy microbumps. In this study, two arranged designs, namely, the distance between critical and dummy joints and the numbers of dummy joints are considered. For the former design, the enlarged view of the outermost location of the microbump array
Conclusions
The presented WLUF process is a promising approach to enhance the mechanical reliability of microbumps during the assembly of a chip-on-chip package. However, the undesired warping induced by the thermocompression procedures of WLUF are seriously influenced by the subsequent stacks of thin chips to generate an apparent plastic strain on the array-type microbumps during a thermal cycling load. To address this issue, this study proposes two layout designs involving the interval between the
Acknowledgments
The authors would like to thank the National Center for High-performance Computing (NCHC) for supporting this research, as well as the National Science Council of Taiwan, R.O.C. for providing financial support under contract number NSC-100-2218-E-033-002-MY2. Likewise, the fabricating support of the specimens from EORL/ITRI is deeply appreciated by the authors.
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