Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats
Introduction
Brain–machine interface (BMI) provides a technological method for persons with damaged sensory and motor functions to restore lost ability or control external devices using their mind (Donoghue, 2002, Wolpaw et al., 2002, Mussa-Ivaldi and Miller, 2003, Lebedev and Nicolelis, 2006, Tonet et al., 2008). This research field has blossomed so spectacularly in recent decades and has led to the proposal of various principles of neural ensemble physiology (Nicolelis and Lebedev, 2009), especially in motor cortical decoding using invasive techniques. Through associating neural activity with its corresponding movement, many groups have realised motor BMIs, such as controlling simple and elaborate robot arms (Chapin et al., 1999, Wessberg et al., 2000, Carmena et al., 2003, Velliste et al., 2008), computer cursors (Serruya et al., 2002, Taylor et al., 2002) and even paralysed muscles (Moritz et al., 2008).
The motor cortical decoding algorithms are of great importance in these applications because they are needed in extracting meaningful information from neural activity in real time (Bashashati et al., 2007). However, because high reliability and processing speed are required, most real-time algorithms are implemented by personal computers (PCs) which limits the applications of designed BMI systems. Even though some wireless neural activity recording systems have been developed (Obeid et al., 2004, Mavoori et al., 2005, Harrison et al., 2007, Ye et al., 2008), a local immobile machine is still needed to predict the output in motor BMIs. With the development of field-programmable gate array (FPGA) and embedded system technique, some portable devices for practical non-invasive BMIs have been developed (Lin et al., 2008), and there is also a tendency to realise the decoding algorithms in a portable device rather than a PC workstation for invasive BMIs. The spike signal processing techniques in invasive BMIs include spike detecting, sorting and mapping, while the performance of mapping algorithm is of the most importance since it extracts the effective information encoded in the spike trains (Kim et al., 2006a). Thus, in this article, we focus on how to implement mapping algorithms in a hardware platform.
Non-linear artificial neural network (ANN) models can optimise each cell's contribution to the population prediction (Schwartz et al., 2001), and some groups demonstrated that this method can successfully track the relationship between neural activity and motor trajectories or parameters. In a previous study in rats (Chapin et al., 1999), a recurrent back-propagation neural network was built to predict lever movement timing and magnitude. Hatsopoulos et al. (2004) designed a two-layer neural network to decode continuous and discrete motor behaviours in behaving monkeys. Kim et al. (2006a) demonstrated the superiority of non-linear mapping in decoding spike trains using multilayer perceptron (MLP) when it was trained by the elaborated procedure of early stopping. Other ANN mapping algorithms, including one hidden-layer feed-forward artificial neural network (Wessberg et al., 2000), learning vector quantisation (LVQ) algorithm (Laubach et al., 2000), time-delay neural network (Kim et al., 2006b) and recurrent MLP (Sanchez and Principe, 2007), have also been described. Sanchez and Principe (2007) suggest that these algorithms should be implemented using the digital signal processor (DSP) hardware for creating the new generation of portable systems. Instead, FPGA computer architectures, which have the characteristic of parallelism, are more suited to implementing ANN models (Omondi and Rajapakse, 2006). Moreover, resource of FPGAs is competitive and rich enough for various ANN applications. FPGA implementation for BMIs has also been suggested by Mak et al. (2006), and many literatures have proposed FPGA implementation of various neural networks for different applications (Chin Tsu et al., 2004, Omondi and Rajapakse, 2006, Pedro et al., 2007, Grossi and Pedersini, 2008, Lin and Tsai, 2008, Lin and Lee, 2009, Lin et al., 2009). However, as far as we know, there is no realisation of mapping algorithms in FPGAs using real spike trains from animals or humans.
Here, we present a portable neural signal processor implemented by FPGAs, which has the advantages of high modularity and high-speed parallel operation compared with other methods. The mapping algorithm we used is a probabilistic neural network (PNN), which approaches Bayesian optimal classification. The operations of both FPGA and Matlab implementations were built and evaluated using real neural signals of rats performing a lever-pressing task for water rewards. The results indicate that the performance of current FPGAs such as the Xilinx Virtex-5 is as accurate as Matlab but the running speed is much faster. It is possible to make practical use of BMIs by the method mentioned in this study.
Section snippets
System setup
A PNN model is realised in an FPGA board (Virtex-5, ML506 board, Xilinx Inc.) for decoding motor cortical neural ensemble recordings in rats performing a lever-pressing task for water rewards (Fig. 1a). The real motor cortical neural signals from rats are recorded by Cerebus™ 128-Channel Data Acquisition System (Cyberkinetics Inc., Salt Lake City, UT, USA) and the pressure signal of the lever is recorded simultaneously. Meanwhile, a PC-based software tool, written in C++, captures the real-time
PNN simulation results on FPGA
The PNN implemented in the FPGA involves 32 inputs, 1000 neurons in the pattern layer, 100 neurons in the summation layer and one output. For each session, the network receives a vector containing 32 neural binned data, and then computes the distances from 1000 training data which belong to 100 classes. After summation and max operation, the output layer exports which class the current neural state maps to. Fig. 7(a) shows the FPGA simulation results, which is compared with Matlab results shown
Application of the system and extension
To the best of our knowledge, an FPGA implementation of motor cortical decoding algorithm has been rarely reported until now. In the previous studies, most of artificial neural network models for decoding in BMIs were realised using Neurosolutions package (Chapin et al., 1999) or Matlab Neural Network Toolbox (Hatsopoulos et al., 2004) or other PC-based software. The FPGA implementation of a probabilistic neural network model that we have proposed provides possibilities for portable BMI
Acknowledgements
This study has received kind and generous support from the National Natural Science Foundation of China (30800287). The authors would like to thank Huaijian Zhang, Qiaosheng Zhang and Xiaochun Liu for helping to tend and train the animals.
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