AEU - International Journal of Electronics and Communications
A simple CMOS-based inductor simulator and frequency performance improvement techniques
Introduction
Inductor simulators find applications in many electronic circuits such as filters, oscillators, biasing and impedance matching. Their electronic tunability by means of a voltage or a current source, high quality factor and wide frequency range of operation make them attractive with respect to physical inductors. Many CMOS-based active inductors which are employed in different applications can be found in the literature [1], [2], [3], [4], [5], [6]. For example, an RF band-pass filter design based on CMOS active inductors has been proposed in [1]. An active tunable inductor employing six CMOS transistor with one control current has been presented in [2]. Alternatively, a wideband tunable active inductor employing four CMOS transistors with a control current and a bias voltage has been reported in [3]. An active inductor with seven CMOS transistors and two control currents has also been developed in [4]. In [5], a noise-cancelling CMOS based active inductor has been implemented. Apart from these, CMOS based active transformers have been proposed in [6]. It should be pointed out that in all of the circuits in [1], [2], [3], [4], [5], [6], current sources are used to tune the simulated inductor.
On the other hand, many inductor simulators constructed with active building blocks such as operational amplifiers (OAs), second-generation current conveyors (CCIIs), current feedback operational amplifiers (CFOAs), and external passive components have been reported [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23]. However they employ a large number of transistors (typically more than 10) and consequently suffer from high power consumption and large area occupation in integrated circuits (ICs). It should be mentioned that the use of only grounded capacitors and external tunability of circuits without requiring passive component matching conditions are important issues in IC design [24], [25], [26], [27].
In this paper, a simple inductor simulator employing only six MOS transistors and a grounded capacitor is presented. The proposed inductor can be tuned electronically by control voltages. Additionally, a CMOS circuit with only four CMOS transistors for realizing negative tunable resistor is developed which can be useful in parasitic cancellation. A novel technique to improve high-frequency performance of inductor simulators is also developed. A new method for providing high frequency performance improvement of simulated inductors is also introduced. The proposed circuit ideas are validated by SPICE program and experimental tests.
Section snippets
Proposed CMOS inductor simulator
Basic CMOS transconductors and inverting amplifiers are used to realize a simple inductor simulator. A simple transconductor using two CMOS transistors and two control voltages is depicted in Fig. 1a. It is assumed that both of the transistors operate in saturation region satisfying the conditions VGS > VTN and VDS > VGS − VTN for M2 (NMOS) besides VSG > |VTP| and VSD > VSG − |VTP| for M1 (PMOS) transistor. Here, VTN and VTP are the threshold voltages of the NMOS and PMOS transistors, respectively.
Low and high frequency improvement methods
Negative impedance converters (NIC) can be used for eliminating the parasitic of simulated inductors and thus enhancing their frequency performance. The NIC symbol shown in Fig. 5 can be divided into two categories, current inversion-type NIC (INIC) with terminal current–voltage relationship as I2 = I1 and V2 = V1, and voltage inversion-type NIC (VNIC) with equations I2 = −I1 and V2 = −V1 [31]. From the NIC (INIC and VNIC) based circuit of Fig. 6, the following input impedance is calculated:
Simulation and experimental results
SPICE simulations of the proposed positive inductor simulator of Fig. 2 are carried out based on 0.13 μm CMOS technology parameters given in [32]. The aspect ratios of all the NMOS and PMOS transistors in Fig. 2 are chosen as 13 μm/1.04 μm and 39 μm/1.04 μm, respectively. As an example, the capacitor of the simulated inductor in Fig. 2 is taken as C = 30 pF. G3 and G4 of the positive inductor simulator with control voltages of VA1 = VA2 = 0.75 V, VB1 = VB2 = 0.55 V and power supply voltages of ±0.75 V are found
Conclusion
In this paper, a simple CMOS inductor simulator is proposed. The suggested inductor simulator includes six MOS transistors and a grounded capacitor; accordingly, it is convenient for IC fabrication. Moreover simple CMOS structures for realizing negative resistor and inductor are also driven. The proposed CMOS negative resistor can be used for elimination of the series parasitic resistances of the inductor simulator and improving its low-frequency performance. A new technique for providing
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