AEU - International Journal of Electronics and Communications
Efficiency of simulation tools in designing sigma–delta ADC
Introduction
In recent years, the design methodology of electronic circuits has changed. Some years ago, integrated circuits were composed adopting graphical tools, by which the basic elements of a circuit were placed in the schematic (bottom-up method). In this way, the generation of a complex circuit was a long process and the resulting schematic was difficult to change and to reuse.
Today, technological improvements in the microelectronic field have led both to the increase of integration density and complexity of electronic circuits. Therefore, the bottom-up methodology is not useful.
Moreover, a short development cycle is a relevant factor for designers in improving the time-to-market and satisfying the customer requirements. Therefore, an automatic instrument is necessary to simplify the work of designers and to predict the real behaviour of complex circuits. As a result, circuit simulation is a fundamental step in design process especially for integrated circuits whose components cannot be modified once manufactured.
However, as simulator resources are limited both in efficiency and in computational complexity, verification could lead to unacceptable simulation times and to algorithm divergences.
To design complex systems that avoid these problems, behavioural modelling has been introduced. Adopting different hardware description languages, various levels of abstraction in modelling systems are possible, such as system level, algorithm description, functional blocks and gate-level net list. Therefore, a top-down design flow is more convenient to adopt.
In this paper, the building blocks of converters are modelled using both Simulink and the VHDL-AMS language. In particular, starting from a true design problem of a modulator, it is shown that two of the most widespread simulation tools, the Simulink and the VHDL-AMS, are both useful for planning and re-arranging design procedure.
In Section 2, the operating principles of conversion, together with the main parameters indicating device performance, are briefly summarized. In Section 3, the characterization of the converter adopting Simulink software package is shown. Section 4 regards VHDL-AMS modelling, while 5 Matlab simulations, 6 VHDL-AMS modelling simulations deal with the comparison between the two tools and the simulation at transistor level.
Section snippets
conversion principles
In Fig. 1, the block diagram of a converter is shown. The feedback loop forces the average value of the quantized signal to track the average input value. The number of integrators gives the order of the converter. The quantizer is modelled as a simple unfixed gain block [1] and a summing block into which the quantization noise is injected. In a single bit converter, the quantizer is a simple comparator.
The output is a digital signal containing a given fraction of the quantization noise
Modelling with Simulink
The first simulation step consists in characterizing the converter adopting Simulink, a software package for modelling and simulating dynamical systems at different levels of abstraction. It supports linear and non-linear systems in both continuous and discrete time. In discrete time mode simulations, the step size is made equal to the sampling period so the simulation time is very short because the new value of a signal is computed only when an event occurs. Using Simulink, the functionality
VHDL-AMS modelling
Electrical simulations of complex systems may become unfeasible in terms of computational resources and elapsed time. For oversampling converters, the performance analysis involves the computation of a large number of samples at the modulator output. This means a very long transient simulation time. In order to reduce the simulation time, behavioural simulations can be performed that lead to reliable results when the behavioural models include contour conditions and sources of error. In
Matlab simulations
For simulations, mathematical models were used, taking into account different non-idealities both for the integrator and for the quantizer [11], [12].
The power spectral density of a sinewave whose amplitude is −3 dB of full scale (FS) obtained with Simulink is represented in Fig. 9 in which the input signal frequency and the noise shaping phenomenon are evident: In this case, the quantization noise is spread out over the signal band.
The third harmonic is due to the non-linearity of the
VHDL-AMS modelling simulations
The complete implementation of the second-order converter is obtained by connecting the models of the different circuits in a runset file.
Different simulations were performed using both OTA and OPAMP amplifiers and the obtained performance is evaluated considering the accuracy of results and flexibility of models.
Conclusions
The continuous development of VLSI technology has led to very high integration density on the same chip. Therefore, it is necessary to have a fast estimation of system performance according to customer requirements. The VHDL-AMS language makes this possible as it permits flexibility in the selection of topology, architectural level simulation and the simulation of the non-idealities of the building blocks of entire structure.
The design criteria of a converter are examined using Matlab and
Maria Rizzi was born in Bari, Italy, in 1965. She received the Dr. Eng. degree and the Ph.D. in 1990 and 1994, respectively. She holds both research and teaching assistantships at the University “Politecnico di Bari”. Her research concerns the analysis and design of electro-optic and all-optic switches for MIN and GSN networks, the analysis and design of all-optical FSMs for ultra-high speed applications, the analysis and design of controllers for photonic networks and the analysis and design
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Maria Rizzi was born in Bari, Italy, in 1965. She received the Dr. Eng. degree and the Ph.D. in 1990 and 1994, respectively. She holds both research and teaching assistantships at the University “Politecnico di Bari”. Her research concerns the analysis and design of electro-optic and all-optic switches for MIN and GSN networks, the analysis and design of all-optical FSMs for ultra-high speed applications, the analysis and design of controllers for photonic networks and the analysis and design of detectors for digital radiography.
Beniamino Castagnolo was born in Palermo, Italy, in 1938. He received the Dr. Eng. degree from the University of Rome in 1963. Since 1965 he has been with the Electronics Department at the Faculty of Engineering of the University “Politecnico di Bari”. Presently he is full professor both of Analog and Digital Electronics. His research interests are in the analysis and design of electro-optic and all-optic switches for MIN and GSN networks, the analysis and design of all-optical FSMs for ultra-high speed applications, the analysis and design of controllers for photonic networks and the analysis and design of detectors for digital radiography.