Test structures and testing methods for electrostatic discharge: results of PROPHECY project
Introduction
Electrostatic discharge represents one of the most critical cause of failure in very high density CMOS integrated circuits [1]. The problem increases dramatically as the device dimensions scale down into the sub-micron range [2], [3]. The development of optimised protection structures against electrostatic discharge (ESD) in sub-micrometer technologies is mandatory and a deep knowledge of the influence of the layout parameters on the ESD robustness itself is needed in order to build robust ESD protection structures.
Currently, most semiconductor manufacturers optimise the protection structures and the intrinsic ESD robustness of the technology by means of test structures. However, a lot of considerations have to be taken into account to chose appropriate test patterns which reflect the real conditions in an I/O circuit of a product. Product requirements as e.g., leakage current requirements, do influence not only the protection structure itself, but also the testing methods and the failure criterion. Particularly, critical are analogue circuits where even a small change in the behaviour of the active device can cause a functional fail of the complete circuit. Other important conditions are e.g., the power supply concept and the coupling between different power supply blocks and the size and the pinning of the chip which influences the length of the power busses. Costly and area consuming test patterns have to be designed in order to evaluate the impact of those factors. A priori it is not clear whether results obtained on single devices (active elements, protection devices) can be transferred directly to the final product.
Another highly debated question is related to the test method used in order to evaluate the device ESD robustness. The most common test methods used are: the Human Body Model (HBM) [4], the Machine Model (MM) [5], and the Charged Device Model (CDM) [6]. For these methods, standards exist or are currently under definition. The ESD robustness levels measured by means of the different test methods are usually quite different so that the possibility of a correlation between the different test methods is still an open question. A standardised, universal test method, if correlated with the usual ones, would be immensely helpful in reducing the work needed for a complete ESD evaluation of the protection structures. Transmission Line Pulsing (TLP) [7] is a further characterisation method which is often used instead of HBM tests for the technology optimisation with respect to the ESD robustness and during the development of the ESD protection structures.
In this work, we present the analysis of a basic set of ESD test patterns, which is used to gain the ESD relevant parameters of active devices and protection structures (see Section 3). Parameters of interest are the failure current obtained with the distinct models, but also the snap-back voltage, holding voltage and the differential resistance in the high-current regime. These parameters determine the protection behaviour of the device. The analysis of the ESD robustness against HBM, TLP and socketed CDM (sCDM) waveform is carried out in great detail for different layout parameter variations. The degree of correlation between TLP and HBM testers and between HBM and sCDM will be presented.
In the second part (see Section 4), the question whether the results obtained on test structures can be applied to product level will be discussed. As an example, for an 0.5 μm analogue technology, results on the basic test structures will be compared with those on more advanced test structures which emulate real pad structures, and finally, with the results of the ESD qualification of several products.
Section snippets
Device description and experimental set-up
Devices studied in this work have been processed by Siemens AG. For the PROPHECY activities, three different technologies have been investigated in order to assure that the conclusions drawn are independent of the technology under investigations. The main features of these processes are summarised in Table 1.
The investigations are mainly concentrated on NMOS transistors. The reason is that the NMOS transistors are used in almost every product as active element in the driver stage. Basically, if
DC characterisation
The devices have been completely DC characterised. In Fig. 2, a typical snap-back curve of a ggNMOS in the 0.35 μm technology is shown. The following parameters are highlighted in the plot: snap-back voltage (threshold Vt voltage), triggering current It (current at the threshold voltage), holding voltage Vh (sustaining voltage), and holding current Ih (current at the holding voltage). The values of Vt, It, Vh, Ih for all the studied devices are compiled in Table 2. Further outputs of the DC
Comparison of results on test patterns with product results
In this section the question whether the results obtained on test structures can be applied at product level will be discussed. As an example, for an 0.5 μm analogue technology, results on the basic test structures will be compared with those on more advanced test structures which emulate real-pad structures, and finally, with the results of the ESD qualification of several products.
A typical example of a pulsed I–V characteristic as it is recorded by TLP measurements on a 200 μm wide NMOS
Conclusions
Standardization of testing procedures and of test vehicles for the evaluation of the ESD hardness of deep submicrometer CMOS technologies is a crucial problem for semiconductor industry. Within the PROPHECY project, we tested a set of test structures, manufactured by SIEMENS using 0.35 and 0,5 μm CMOS technologies based on grounded-gate NMOS, and a 0,5 μm analog CMOS process including different protection devices (e.g. bipolar). We aimed at: (i) comparing different testing methods, identifying
Acknowledgements
We appreciate the Work supported by the Standard Measurements and Testing E.C. programme under the contract number SMT4-CT95-2020 (PROPHECY). The work was also partially supported by CNR Italy P.F. MADESS II.
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