Effect of design considerations on productivity at wafer level

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Abstract

This paper examines the effect on yield and productivity of design considerations such as packing density, levels of vertical integration, minimum design dimensions, and chip size. Expressions are presented to calculate the number of circuits on chips of different design, the initial and later yield, the time interval needed for two different products to attain the same yield, the rate of defect density reduction needed to meet a desired yield in a prescribed time period, and the productivity of different designs.

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Based on a paper presented at RELECTRONIC'91, the 8th Symposium on Reliability in Electronics, Budapest, Hungary, August 26–30, 1991.

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