Effect of design considerations on productivity at wafer level☆
References (15)
Parameters for Optimization of Productivity at Wafer Level
IEEE Transactions on Electron Devices
(April 1992)An Algebraic Expression to Count the Number of Chips on a Wafer
IEEE Circuits and Devices Magazine
(January 1989)Defects, Faults and Semiconductor Yield
- et al.
A Discussion of Yield Modeling with Defect Clustering, Circuit Repair and Circuit Redundancy
IEEE Transactions on Semiconductor Manufacturing
(August 1990) Fact and Fiction in Yield Modeling
Microelectronics Journal
(1989)On the Assumptions contained in Semiconductor Yield Models
IEEE Transactions on Computer-Aided Design of Circuits and Systems
(August 1992)Fault Probability and Critical Area in VLSI Yield Projection
IBM Technical Report TR19.0562
(January 1982)
There are more references available in the full text version of this article.
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Based on a paper presented at RELECTRONIC'91, the 8th Symposium on Reliability in Electronics, Budapest, Hungary, August 26–30, 1991.
Copyright © 1994 Published by Elsevier Ltd.