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Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter

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Abstract

Designing embedded systems is a challenging task during which wrong choices can lead to extremely costly re-design loops, especially when these wrong choices are made during the algorithm specification and the mapping over the selected architecture. In this paper we propose a high-level approach for design space exploration, using a usual standard language as input. More precisely we present the two first steps of the Design Trotter framework: (i) the specification step and its underlying internal model (HCDFG: Hierarchical and Control Data Flow Graph) and (ii) the characterization step which takes place very early in the design flow. Indeed, once transformed into our internal representation, the specification is rapidly and automatically characterized and explored at the algorithmic level. The framework provides the designer with metrics so that he can evaluate, very early in the design process, the impact of algorithmic choices on resource requirements in terms of processing, control, memory bandwidth and potential parallelism at different levels of granularity. The overall aim of our approach is to improve the algorithm/architecture matching that sorely influences the implementation efficiency in terms of silicon area, performances and energy consumption. We give examples which illustrate how designers can refer to the outcomes of the Design Trotter framework in order to select or build suitable architectures for specific applications.

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References

  1. Y. Le Moullec, J-Ph. Diguet, and J.-L. Philippe, “Design-trotter: a Multimedia Embedded Systems Design Space Exploration tool,” in IEEE Workshop on Multimedia Signal Processing (MMSP 2002), St. Thomas, US Virgin Islands, December 2002.

    Google Scholar 

  2. Th. Gourdeaux, J-Ph. Diguet, and J.-L. Philippe, “Design trotter: Interfunction cycle Distribution Step,” in 11th Int. Conf. RTS Embedded Systems, Paris, France, April 2003.

  3. S. Bilavarn, G. Gogniat, J.L. Philippe, and L. Bossuet, “Fast Prototyping of Reconfigurable Architectures > from a c Program,” in ISCAS 2003, Bangkok, Thailand, May 2003.

  4. L. Bossuet, W. Burleson, G. Gogniat, V. Anand, A. Laffely, and J.L. Philippe, “Targeting Tiled Architectures in Design Exploration,” in 10th Reconfigurable Architectures Workshop (RAW), Nice, France, April 2003.

    Google Scholar 

  5. A. Azzedine, J-Ph. Diguet, and J.-L. Philippe, “Large exploration for hw/sw partioning of multirate and aperiodic real-time systems,” in International Symposium on Hardware/Software Codesign (CODES), Estate Park, USA, May 2002.

  6. Gérard Berry, “The esterel primer,” http://www-sop.inria.fr/meije/esterel/esterel-eng.html.

  7. N. Halbwachs, Synchronous Programming of Rective Systems, Kluwer Academic Publisher, 1993.

  8. F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki, and B. Tabbara, Hardware-Software Co-Design of Embedded Systems: The Polis Approach, Kluwer Academic Publisher, June 1997.

  9. S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, “Design of embedded systems: formal models, validation and synthesis,” in Proceedings of the IEEE, March 1997.

  10. J. Buck and E.E. Lee, “, the token flow model,” in Data Flow Workshop, Hamilton Island, Australia, May 1992.

  11. A.D. Pimentel, L.O. Hertzberger, P. Lieverse, P. van der Wolf, and Ed F. Deprettere, “Exploring embedded-systems architectures with artemis,” IEEE Computer, vol. 34, no. 11, 2001, pp. 57–63.

    Article  Google Scholar 

  12. “Ptolemy project webpage,” http://ptolemy.eecs.berkeley.edu/.

  13. “Systemc web page,” http://www.systemc.org/.

  14. A. Gerstlauer and D. Gajski, “System level abstraction semantics,” in IEEE International Symposium on System Synthesis (ISSS), Kyoto, Japan, 2002.

  15. L. Cai, S. Verma, and D.D. Gajski, “Comparison of specc and systemc languages for system design,” Tech. Rep. CECS-03-11, Univ. of California, Irvine, Irvine, USA, 2003.

    Google Scholar 

  16. “Esterel studio web page,” http://www.esterel-technologies.com/.

  17. L. Guerra, M. Potkonjak, and J. Rabaey, “System-level design guidance using algorithm properties,” in IEEE Workshop on VLSI Signal Processing, San Diego, USA, Oct. 1994.

  18. J-Ph. Diguet, O. Sentieys, J.-L. Philippe, and E. Martin, “Probabilistic resource estimation for pipeline architecture,” in IEEE Workshop on VLSI Signal Processing, Sakai, Japan, Oct. 1995.

  19. F. Vahid and D. D. Gajski, “Closeness metrics for system-level functional partitioning,” in EDAC, Brighton, U.K., Sept. 1995, pp. 328–333.

  20. L. Carro, M. Kreutz, F. Wagner, and M. Oyamada, “System synthesis for multiprocessor embedded applications,” in Design Automation and Test in Europe Conference (DATE), Paris, France, March 2000.

  21. D. Sciuto, F. Salice, L. Pomante, and W. Fornaciari, “Metrics for design space exploration of heterogeneous multiprocessor embedded systems,” in International Symposium on Hardware/Software Codesign (CODES), Estes Park, USA, May 2002.

  22. M. Auguin, K. Ben Chehida, J-Ph. Diguet, X. Fornari, A-M. Fouilliart, C. Gamrat, G. Gogniat, P. Kajfasz, and Y. Le Moullec, “Partitioning and codesign tools & methodology for reconfigurable computing: The epicure philosophy,” in 3rd Int. Work. on Systems, Architectures, Modeling Simulation (SAMOS03), Greece, July 2003.

  23. A. Dasdan, D. Ramanathan, and R.K. Gupta, “Rate derivation and its application to reactive real-time embedded systems,” in 35th Acm/IEEE Design Automation Conf., San Francisco, USA, 1998.

  24. M. Miranda, M. Janssen, F. Catthoor, and H. De Man, “ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures,” in 9th IEEE/Acm Int. Symp. on System Synthesis, La Jolla, USA, Nov. 1996.

  25. S. Wuytack, J-Ph. Diguet, F. Catthoor, and H. De man, “Formalized methodology for data reuse exploration for low-power hierarchical memory mappings,” IEEE Transaction on VLSI Systems, vol. 6, no. 4, 1998, pp. 529–537.

    Article  Google Scholar 

  26. Y. Le Moullec, J-Ph. Diguet, D. Heller, and J.-L. Philippe, “Fast and adaptive data-flow and data-transfer scheduling for large design space exploration,” in Great Lakes Symposium on VLSI (GLSVLSI), New-York, USA, April 2002.

  27. M. Antonini, M. Barlaud, P. Mathieu, and I. Daubechies, “Image Coding Using Wavelet Transform,” IEEE Transaction on Image Processing, vol. 1, no. 2, 1992, pp. 205–206.

    Article  Google Scholar 

  28. S. Bilavarn P. Vandergheynst E. Debes, “Methodology and Tools to Define Special Purpose Processor Architecture,” http://ltswww.epfl.ch/bilavarn/SpecialPurposeProcessor_files/frame.htm, 2003, Intel grant 11409.

  29. L. Letellier and E. Duchesne, “Motion Estimation Algorithms,” Tech. Rep., L.C.E.I, C.E.A, Saclay, France, 2001.

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Correspondence to Jean-Philippe Diguet.

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Yannick Le Moullec received the M.S degree from the University of Rennes (France) in 1999 and the Ph.D degree from the University of South Brittany (France) in 2003. His thesis focused on Hardware/Software codesign, and more specifically on high-level design space exploration of embedded systems. His thesis work is part of the EDA framework “Design Trotter”. In 2003 he joined the center for embedded software (CISS) at Aalborg University (Denmark) as a post-doc fellow. His current work deals with design space exploration for wireless applications.

Jean-Philippe Diguet received the M.S degree and the Ph.D degree from Rennes University (France) in 1993 and 1996 respectively. His thesis, carried out at LASTI lab., focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. He has been a member of the LESTER lab. (Lorient, France) since 1998, where he initiated a research project in design space exploration both at the algorithmic and system levels. He has been an associated professor at the University of South Brittany (France) from 1998 until 2002. In 2002, he initiated a technology transfer and co-funded Dixip, a company in the domain of wireless embedded systems. Since 2004 he is a CNRS (French National Scientific Research Center) researcher. His work focuses on two topics. The first one is the management of the development of the EDA framework “Design Trotter” for design space exploration and combining the design space exploration with technology mapping over reconfigurable architectures. The second topic is the definition of environment-aware, predictive and self-adaptive architectures under QoS and power constraints, this topic includes new OS services, NOCs and architecture reconfiguration control.

Nader Ben Amor is a PhD student at both University of South Brittany (France) and Sfax Engineering School (Tunisia). He received the Electrical Engineering Diploma in 2000 and the M.S Degree in Electronics in 2001 from Sfax Engineering School. His research interest is the design of embedded multimedia processors.

Thierry Gourdeaux received the Engineer Title and the M.S degree from the ENSSAT school, Lannion (France), in 1997. Since 1999 he is a research engineer at the University of South Brittany. His work includes the analysis of DSP systems for spatial applications (with Alcatel Espace), technology and knowledge transfers to the industry community and the development of EDA tools such as “Design Trotter” and “Soft Explorer”.

Jean-Luc Philippe is currently a full Professor at the University of South Brittany (France). He is leading a research group working on design methodologies for electronic systems executing under performances, consumption and safety constraints. Once implemented into tools, these methodologies are applied to several domains: signal and image processing, telecommunications, transitic systems, etc.

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Le Moullec, Y., Diguet, JP., Amor, N.B. et al. Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter. J VLSI Sign Process Syst Sign Image Video Technol 42, 185–208 (2006). https://doi.org/10.1007/s11265-005-4181-x

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