This special issue contains extended papers of the 57th International Midwest Symposium on Circuits and Systems, selected by the Guest Editors based on reviewers’ comments, attendees paper grading and session chair recommendations. The International Midwest Symposium on Circuits and Systems is the oldest Circuits and Systems Symposium sponsored by the IEEE CAS Society. This conference contributes to its strong history by reporting the latest research results and innovations in the field of circuits and systems through Distinguished Speakers featuring the newest innovations relevant to this field and shedding light on its evolution towards breaching the gaps among technologies. MWSCAS-2014 received 336 paper submissions from 32 countries. The papers were evaluated by a minimum of three reviewers. Among all these contributions, a subset of these papers were invited for this special issue. The invited papers went through a peer review process consisting of world recognized experts in related fields. After a long journey, 15 papers were finally accepted.

In the first paper, Tripurari et al., propose a wide-band RF channelizer architecture that splits the 0.6-9 GHz input spectrum in seven channels of 1.2 GHz each. The architecture enables multi-Gbps aggregate data reception with the property of agile switching between channels. The average power consumption is only 435 mW while achieving a dynamic range between 58 and 63 dB. Two compact switchless dual-band load networks for class-E power amplifier (PA) operating at 800 and 1900 MHz are reported by Li et al. The PA with transformer-based load network achieves an outstanding power added efficiency of 68.6 % at low band and 62.6 % at high band at an output power of 37.8 and 36.7 dBm, respectively. The LC-based PA shows a similar PAE of 68.3 and 60 % at low band and high band, respectively. A MIMO satellite communication system with accelerated dual paths (ADP) asynchronous design authored by Che et al., reports an asynchronous design approach for multiple input multiple output satellite communication systems. Authors employ an ADP design; the data flow between the two paths, the increase the reliability of the system by circumventing transient faults induced delay. The proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle. Ming et al., present a receive-side circuitry that merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments. The techniques are demonstrated in a prototype fabricated in a 65-nm CMOS process demonstrating effective crosstalk cancellation at 10 Gb/s.

Optimal two-stage comb decimators are reported by Salgado et.al. Authors show how to choose the decimation factor of the first stage in order to get simultaneously the best possible power reduction with optimal area tradeoff, in a comparison with a single cascade integrator-comb architecture. The issues related to susceptibility to supply noise in class D amplifiers are analyzed by He and co-authors. In this paper, the class D PSRR is analytically investigated; the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA. The derived analytical expressions are verified by means of HSPICE simulations and on measurements on discretely-realized CDAs. Damera et al., propose the use of minimally invasive filters. third order and fourth order filters are designed in 130 nm technology; when compared with the conventional filter implementations such as a Tow-Thomas architecture, the proposed third order solution achieves a total in-band input-referred integrated noise of 44 µV compared to 79 µV achieved by a Tow-Thomas implementation. In addition, lower power consumption is claimed. Soto Aguilar and coauthors introduce a methodology to reduce the distortion introduced by the harmonics of the clock in the operation of switched-R-MOSFET-C filters. The clock harmonic cancellation technique shows an improvement of more than 38 dB without compromising the tuning range or requiring increasing the frequency of the clock. The techniques are demonstrated employing a standard CMOS IBM 180 nm. Chang and Onabajo report an instrumentation amplifier architecture with a mechanism that generates negative capacitances at its input that allows adaptive cancellation of the input capacitances from the electrode cables and printed circuit board. The proposed negative capacitance generation technique can improve the input impedance. An operational transconductance amplifier that achieves a transconductance of 25 pS and very high output impedance is described.

Power management is another relevant area that is becoming more and more relevant. Cong and Lee report a techniques that promises to improve the power efficiency for high-voltage DC-DC converters employing high switching frequencies. A two-phase quasi-square-wave zero-voltage-switching (PS-TPZVS) cell is used to realize ZVS operation for all power FETs. The proposed design saves one auxiliary inductor and one auxiliary capacitor and thus reduces both the volume and power losses of the auxiliary circuitry. It is verified through simulations that peak efficiencies over 95 % are feasible. Teh et al., report an energy harvesting scheme that generates bipolar output voltage (±1 V). The architecture is based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. Designed in a standard CMOS 0.13–l m technology, chip chi functionality is verified. At start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW. A 0.75 V supply nanowatt resistorless sub-bandgap CMOS voltage reference is reported by Caicedo et al. The circuit uses a curvature compensation technique that allows higher temperature stability. Simulation results in 180 nm CMOS process, for a voltage of 469 mV shows a temperature coefficient of 5 ppm/°C for the -40–125 °C extended temperature range. A microwatt voltage doubler-based voltage regulator for ultra-low power energy harvesting systems is reported by J. Salomaa et al. The architecture is based on switched-capacitor techniques and produces a stable 1.2-V power supply using inputs from 0.63 to 1.8 V. Implemented in a 180 nm CMOS process, the regulator achieves a regulator peak power and current efficiency are 63 and 49 %, respectively. Ture et al., developed a low-power pulse position modulation demodulator intended for remotely powered battery-less implant-table devices. The power for the implantable device is provided by the magnetic coupling employing external coils. Fabricated in a 0.18 lm CMOS technology, the experimental results verify the functionality of the PPM demodulator.

In the last paper, Shi et al., propose an optimization based on genetic algorithm in order to select the most suitable speed-sensors for speed binning. Authors demonstrate that optimizing sensor selection can improve speed-binning accuracy. The optimization algorithm shows improving accuracy beyond 94 and 93 %, respectively.

The Editors would like to recognize the support of the Organizing Committee of the 57th MWSCAS, Conference Steering Committee, Session Chairs, anonymous reviewers and special thanks to the authors. We hope you will enjoy reading these papers and find them useful for your future research endowments.