Abstract
A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430–435 MHz PLL for frequency synthesizing, a 1.72–1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are −19.9 and −20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are −61.2 dBc@20 MHz and −57.7 dBc@40 MHz at the output of the PLL, and −70.5 dBc@20 MHz and −66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.
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References
Annamalai, A. M., Kok, F. O., Yeung, B. C., & Wooi, G. Y. (2006). A 2.4-GHz CMOS RF front-end for wireless sensor network applications. In IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (4 pp).
Boom, N., Rens, W., & Crols, J. (2004). A 5.0mW 0 dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOS. In Proceeding of the 30th European, solid-state circuits conference (pp. 199–202). Leuven, Belgium.
Cao, C., & Kenneth, K. O. (2005). A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS. IEEE Microwave and Wireless Components Letters, 15(11), 721– 723.
Cheng, S., Tong, H., Silva-Martinez, J., & Karsilayan, A. I. (2007). A fully differential low-power divide-by-8 injection-locked frequency divider up to 18 GHz. IEEE Journal of Solid-State Circuits, 42(3), 583–591.
Cook, B. W., Berny, A., Molnar, A., Lanzisera, S., & Pister, K. S. (2006). Low-power 2.4-GHz transceiver with passive RX front-end and 400-mV supply. IEEE Journal of Solid-State Circuits, 41(12), 2757–2766.
Craninckx, J., & Steyaert, M. S. (1996). A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μ m CMOS.IEEE Journal of Solid-State Circuits, 31(7), 890–897.
Deen, M., Murji, R., Fakhr, A., Jafferali, N., & Ngan, W. (2005). Low-power CMOS integrated circuits for radio frequency applications. Circuits, Devices and Systems. IEE Proceedings, 152(5), 509–522. doi:10.1049/ip-cds:20045069.
Ding, Y., & Kenneth, K. O. (2007). A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS. IEEE Journal of Solid-State Circuits, 42(6), 1240–1249.
Fan-Hsiu, H., & Yi-Jen. C. (2006). V-band CMOS differential-type injection locked frequency dividers. In 2006 International symposium on VLSI design, automation and test (pp. 1–2).
Feng, Z., Xiaoping, G., Huajiang, Z., Kangmin, H., & Zhiliang, H. (2009). A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL. In IEEE 10th annual wireless and microwave technology conference (pp. 1–4). Sand Key Beach, Clearwater
Ferriss, M. A., & Flynn, M. P. (2008). A 14 mW fractional-N PLL modulator with a digital phase detector and frequency switching scheme. IEEE Journal of Solid-State Circuits, 43(11), 2464–2471.
Gu, Q. (2005). RF system design of transceivers for wireless communications. New York: Springer.
Ka, F. C., & Cheng, K. K. (2008). Low power quadrature-input programmable frequency divider. In Asia-Pacific Microwave Conference (pp. 1–4).
LAN/MAN Standards Committee of the IEEE Computer Society. (2003). Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs). New York: IEEE std. 802.15.4.
Margarit, M., Tham, J. L., Meyer, R., & Deen, M. (1999). A low-noise, low-power VCO with automatic amplitude control for wireless applications. IEEE Journal of Solid-State Circuits 34(6), 761–771. doi:10.1109/4.766810.
McMahill, D. R., & Sodini, C. G. (2002). A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated ΣΔ frequency synthesizer. IEEE Journal of Solid-State Circuits, 37(1), 18–26.
Pellerano, S., Levantino, S., Samori, C., & Lacaita, A. L. (2004). A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE Journal of Solid-State Circuits, 39(2), 378– 383.
Peng, K. C., Huang, C. H., Li, C. J., Horng, T. S., & Lee, S. F. (2006). Design of a CMOS VCO with two tuning inputs applied for a wideband GFSK-modulated frequency synthesizer. In IEEE radio and wireless symposium (pp. 443–446).
Perrott, M. H., Tewksbury, T. L., & Sodini, C. G. (1997). A 27-mW CMOS fractional-N synthesizer using digital compensation or 2.5-Mb/s GFSK modulation. IEEE Journal of Solid-State Circuits, 32(12), 2048–2060.
Rahajandraibe, W., Zaid, L., Cheynet, B. V., & Bas, G. (2007). Frequency synthesizer and FSK modulator for IEEE 802.15.4 based applications. In 2007 IEEE radio frequency integrated circuits (RFIC) symposium (pp. 229–232).
Razavi, B. (2000). Design of analog CMOS integrated circuits. Beijing: Tsinghua University Press.
Shen, W., Yang, Y., Wang, F., & Hong, Z. (2006). Gaussian frequency shift keying for Bluetooth. Research and Progress of SSE, 26(3), 111–115.
Shu, K., & Sanchez-Sinencio, E. (2002). A 5-GHz prescaler using improved phase switching. In IEEE international symposium on Circuits and systems (Vol. 3, pp. III–85–III–88).
Steyaert, M., & Crols, J. (1997). CMOS wireless transceiver design. Norwell: Kluwer.
Takahashi, M., Ogawa, K., & Kundert, K. S. (1999). VCO jitter simulation and its comparison with measurement. In Proceedings of the Asia and South Pacific design automation conference (Vol. 1, pp. 85–88).
Vaucher, C. S., Ferencic, I., Locher, M., Sedvallson, S., Voegeli, U., & Wang, Z. (2000). A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. IEEE Journal of Solid-State Circuits, 35(7), 1039–1045.
Willingham, S., Perrott, M., Setterberg, B., Grzegorek, A., & McFarland, B. (2000). An integrated 2.5 GHz ΣΔ frequency synthesizer with 5 μs settling and 2 Mb/s closed loop modulation. In IEEE international solid-state circuits conference, Digest of technical papers (pp. 200–201, 457).
Yao-Hong, L., & Tsung-Hsien, L. (2007). An energy-efficient 1.5-Mbps wireless FSK transmitter with a ΣΔ modulated phase rotator. In 33rd European solid state circuits conference (pp. 488–491).
Yueh-Hua, Y., & Chen, Y. J. (2008). Ring-based direct injection-locked frequency divider in display technology. IEEE Microwave and Wireless Components Letters, 18(11), 752–754.
Zhao, B., Mao, X., Yang, H., & Wang, H. (2008). A 1.41-1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler. Analog Integrated Circuits and Signal Processing, 59(3), 1573–1979 (on line).
Zheng, H., & Luong, H. C. (2008). Ultra-low-voltage 20-GHz frequency dividers using transformer feedback in 0.18-μm CMOS process. IEEE Journal of Solid-State Circuits, 43(10), 2293–2302.
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Zhao, B., Guo, L., Yang, H. et al. A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz. Analog Integr Circ Sig Process 67, 293–308 (2011). https://doi.org/10.1007/s10470-011-9611-z
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DOI: https://doi.org/10.1007/s10470-011-9611-z