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Single-electron transistor: review in perspective of theory, modelling, design and fabrication

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Abstract

Integrated circuit (IC) technology has grown tremendously over the last few decades. The prime goal has been to achieve low-power and high-performance in logic and memory devices with minimal footprint. This has lead to continuous scaling of devices and interconnects over silicon chips. Scaling of technology plays an important role for improvement of IC performance in terms of delay, signal-integrity and power-dissipation. Novel devices like FinFET, nano-electromechanical systems, graphene-FETs and single-electron transistor (SET) offer several advantages over various shortcomings of scaling. The future of IC industry is proposed to be heterogeneous 3D integration of different technologies. A SET is a potential nano device that works on quantum mechanical principle and can be co-integrated with the widely adopted complementary metal-oxide semiconductor technology to enhance its performance at scaled technology nodes. To explore the feasibility of SET, an extensive literature review has been carried out in this paper. The literature review comprises comprehensively research work related to SET theory, design and fabrication. Also, the SET based computing system design is presented for room temperature operation. The extensive literature review and thereafter execution of varying analyses reveal that the SET is a potential nano-device for futuristic applications.

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  1. Space Applications Centre (ISRO) SEPD/SEG/SEDA, Ahmedabad, Gujarat, India

    Rashmit Patel

  2. Dhirubhai Ambani Institute of Information and Communication Technology DA-IICT, Gandhinagar, Gujarat, India

    Yash Agrawal & Rutu Parekh

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  1. Rashmit Patel
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Patel, R., Agrawal, Y. & Parekh, R. Single-electron transistor: review in perspective of theory, modelling, design and fabrication. Microsyst Technol 27, 1863–1875 (2021). https://doi.org/10.1007/s00542-020-05002-5

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