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Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

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Abstract

Static random access memory (SRAM) cell design has undergone extensive development to achieve good performance and low power consumption. This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation. The Schmitt-trigger (ST)-based inverter and PPN-inverter are coupled back to back to create the novel SRAM cell structure. Additionally, single-ended writing, feed-back cutting, and single-ended reading are used in this novel SRAM cell. The single-ended writing technique and feed-back cutting method are used to their full potential to increase the write static noise margin (WSNM) of this 10 T CNTFET SRAM cell. The single-ended read mode of this 10 T CNTFET SRAM cell increases the read static noise margin (RSNM) as the storage nodes are not disturbed. The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDDmin of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of this introduced SRAM cell and several existing SRAM cells are simulated and the parameters are compared. A comparative study shows that the introduced cell is more stable than the other cells while consuming less power during reading and holding. Furthermore, the new cell reads much faster and has less VDDmin than the other bit cells. This research also documents how SRAM cell performance changes when the CNTFET parameters change. Using the 32 nm CNTFET model from Stanford University using the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulation tool, the simulation is carried out.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Government College of Engineering, Srirangam, Trichy, Tamilnadu, India

    M. Elangovan

  2. VLSI Centre of Excellence, Chitkara University Institute of Engineering and Technology, Chitkara University, Punjab, India

    Kulbhushan Sharma

  3. Chitkara University Institute of Engineering and Technology, Chitkara University, Punjab, India

    Ashish Sachdeva & Lipika Gupta

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Correspondence to M. Elangovan.

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Elangovan, M., Sharma, K., Sachdeva, A. et al. Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications. Circuits Syst Signal Process 43, 1627–1660 (2024). https://doi.org/10.1007/s00034-023-02529-6

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