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Decimal Square Root: Algorithm and Hardware Implementation

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Abstract

We propose a new digit recurrence decimal square root (DSR) design and provide its ASIC implementation. The interim square root digits are in \([ {-5,5} ]\). The proposed architecture generally follows that of a previous radix-10 divider. However, it provides novel solutions with regard to few DSR-specific challenges. For example, complex error analysis shows that only four (out of sixteen) digits of partial square root is sufficient to estimate partial remainders that are required for the more complicated square root digit selection. This design performs about 10 % faster and consumes 28 % less area than the previously reported ASIC digit recurrence decimal square rooter.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Shahid Beheshti University, Evin, 19839-63113, Iran

    Adel Hosseiny & Ghassem Jaberipur

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  1. Adel Hosseiny
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  2. Ghassem Jaberipur
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Correspondence to Ghassem Jaberipur.

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Hosseiny, A., Jaberipur, G. Decimal Square Root: Algorithm and Hardware Implementation. Circuits Syst Signal Process 35, 4195–4219 (2016). https://doi.org/10.1007/s00034-015-0215-1

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  • DOI: https://doi.org/10.1007/s00034-015-0215-1

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