Abstract
We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.
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References
F. Gardner, Charge pump phase-lock loops. IEEE Trans. Commun. 28(11), 1849–1858 (1980)
B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, New York, NY, 2001)
W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops, in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS 1999, Orlando, FL, USA, pp. 554–557 (1999)
J. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE J. Solid-State Circuits 31(11), 1723–1732 (1996)
C. Zhang, T. Au, M. Syrzycki, A high performance NMOS-switch high swing cascode charge pump for Phase-locked loops, in IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, USA, pp. 554–557, 5–8 Aug 2012
M. Estebsari, M. Gholami, M.J. Ghahramanpour, A novel charge pump with low current for low-power delay-locked loops. Circuits Syst. Signal Process. 36(9), 3514–3526 (2017)
M. Shiau, H. Hsu, C. Cheng, H. Weng, H. Wu, D. Liu, Reduction of current mismatching in the switches-in-source CMOS charge pump. Microelectron. J. 44(12), 1296–1301 (2013)
K.K.A. Majeed, B.J. Kailath, Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP. Analog Integr. Circ. Sig. Process 93(1), 29–39 (2017)
E. Juarez-Hernandez, A. Diaz-Sanchez, A novel CMOS charge pump circuit with positive feedback for PLL applications, in IEEE International Conference on Electronics, Circuits and Systems, pp. 349–352 (2001)
V. Sujatha, R.S.D. Banu, R. Sakthivel, M. Vanitha, Phase-locked loop with high stability against process variation and gain-boosting charge pump for current matching characteristics. Eur. J. Sci. Res. 46, 431–442 (2010)
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Saldanha, A., Gupta, V., Joshi, V.K. (2019). Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 900. Springer, Singapore. https://doi.org/10.1007/978-981-13-3600-3_65
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DOI: https://doi.org/10.1007/978-981-13-3600-3_65
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