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A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \(\upmu \)m CMOS

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

This work presents the design of ultra low power (ULP) management unit to be used in conjunction with tiny solar cells or energy harvesters providing very low power for wireless sensor node (WSN) applications for energy autonomy. The power management unit (PMU) is implemented using \(0.18\,\upmu \)m CMOS in subthreshold region of MOSFET for reduced power consumption with increased efficiency. It regulates the output voltage at 0.95 V and 0.968 V when the input voltages are 0.98 V and 1.33 V, respectively and achieves maximum 72.3% efficiency. The proposed PMU consumes 36 nW and 56 nW of power, at input voltages of 0.98 V and 1.33 V, respectively, thereby making it suitable for ultra low voltage, low power applications.

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Correspondence to Purvi Patel or Biswajit Mishra .

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Patel, P., Mishra, B., Nagchoudhuri, D. (2017). A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \(\upmu \)m CMOS. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_47

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_47

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

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