Abstract
This paper presents an in-depth analysis of the propagation delay of dynamic CMOS latches and its variability when subjected to process, voltage and temperature (PVT) variations. Three basic topologies namely the cascade voltage switch logic (CVSL), dynamic single transistor clocked (DSTC) and dynamic ratio insensitive (DRIS) have been investigated for robustness and switching characteristics. The extensive analysis provides well-defined guidelines for selection of variation-aware CMOS latches used in digital logic design. All simulations have been performed on 180 nm TSMC industry standard technology node using SPICE circuit simulator.
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References
Jiren Yuan, Christer Svensson, “New Single Clock CMOS Latches and Flip Flops with Improved Speed and Power Savings,” IEEE Journal of Solid State Circuit, vol. 32, no. 1, pp. 62–69, January 1997.
B. Dally, “Architectures and circuits for energy-efficient computing,” keynote speech.at the CICC, September 2012.
Massimo Alioto, Gaetano Palumbo, Melita Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” IEEE Transactions on Very Large Scale Integration (VLSI) System, vol. 18, no. 5, pp. 697–710, 2010.
F. Hassan,W. Vanderbauwhede, F. Rodríguez-Salazar, “Impact of random dopant fluctuations on the timing characteristics of flip-flops,” IEEE Transactions on Very Large Scale Integration (VLSI) System, vol. 20, no. 1, pp. 157–161, 2012.
M. Alioto, G. Palumbo, M. Pennisi, “A simple circuit approach to reduce delay variations in domino logic gates,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 10, pp. 2292–2300, 2012.
Alioto M., Consoli E., Palumbo G., “Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, issue: 8, pp. 2035−2043, 2015.
Alioto M., Consoli E., Palumbo G., “Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, issue: 3, pp. 835−843, 2015.
Massimo Alioto, Gaetano Palumbo, “Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, issue: 12, pp. 1322–1335, 2006.
Ahmadi R., Najm F.N., “Timing analysis in presence of power supply and ground voltage variations,” IEEE International Conference on Computer Aided Design (ICCAD), pp. 176–183, 2003.
Neelam Arya, Shweta Singh, Manisha Pattanaik, “Temperature Insensitive Design For Power Gated Circuits,” 9th International Conference on Industrial and Information Systems (ICIIS), pp. 1–6, 2014.
Sakurai T., Newton A.R., “Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas,” IEEE Journal of Solid-State Circuits, vol. 25, issue: 2, pp. 584−594, 1990.
Kanda K., Nose K., Kawaguchi H., Sakurai T., “Design Impact of Positive Temperature Dependence on Drain Current in Sub-1-V CMOS VLSIs,” IEEE Journal of Solid-State Circuits, vol. 36, issue: 10, pp. 1559−1564, 2001.
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Rishab Mehra, Swapnil Sourav, Aminul Islam (2017). Cross-Coupled Dynamic CMOS Latches: Robustness Study of Timing. In: Mandal, J., Satapathy, S., Sanyal, M., Bhateja, V. (eds) Proceedings of the First International Conference on Intelligent Computing and Communication. Advances in Intelligent Systems and Computing, vol 458. Springer, Singapore. https://doi.org/10.1007/978-981-10-2035-3_32
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DOI: https://doi.org/10.1007/978-981-10-2035-3_32
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