Abstract
The research article proposed the 3D mesh topological network on chip (NoC) and its hardware chip implementation. 3D NoC improves the performance of on-chip communication network because the connection of the switches and their length to connecting links is shorter and the data can be switched across the on-chip communication network with the help of less number of switches. The cluster size of the designed 3D mesh NoC is chosen as 4 × 4 × 4. The addressing scheme and intercommunication among nodes is verified in the scalable design. The proposed 3D mesh NoC is designed with the help of VHDL programming language, simulated in ModelSim 10.1 and synthesized in Xilinx ISE 14.2 as software tools. The communication is realized based on look ahead XYZ routing algorithm. The targeted FPGA is Virtex-5 and hardware and timing parameters are also analyzed in the same design.
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Arpit Jain, Rakesh Dwivedi, Adesh Kumar, Sanjeev Sharma (2017). Scalable Design and Synthesis of 3D Mesh Network on Chip. In: Singh, R., Choudhury, S. (eds) Proceeding of International Conference on Intelligent Communication, Control and Devices . Advances in Intelligent Systems and Computing, vol 479. Springer, Singapore. https://doi.org/10.1007/978-981-10-1708-7_75
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DOI: https://doi.org/10.1007/978-981-10-1708-7_75
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