Abstract
The CMOS technology has dominated the mainstream silicon IC industry in the last few decades. As CMOS integrated circuits are moving into unprecedented operating frequencies and accomplishing unprecedented integration levels (Fig. 1.1), potential problems associated with device scaling—the short-channel effects—are also looming large as technology strides into the deep-submicron regime. Besides that it is costly to add sophisticated process options to control these side effects, the compact device modeling of short-channel transistors has become a major challenge for device physicists.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
L.W. Liebmann et al., TCAD development for lithography resolution enhancement. IBM J. Res. Dev. 45, 651–665 (2001)
R.W. Keyes, The impact of randomness in the distribution of impurity atoms on FET threshold. J. Appl. Phys. 8, 251–259 (1975)
T.B. Hook et al., Lateral ion implant straggle and mask proximity effect. IEEE Trans. Electron Devices 50(9), 1946–1951 (2003)
V. Moroz, L. Smith, X.-W. Lin, D. Pramanik, G. Rollins, Stress-aware design methodology, in IEEE International Symposium on Quality Electronic Design, 2006
P.J. Timans, et al., Challenges for ultra-shallow junction formation technologies beyond the 90 nm node, in International Conference on Advances in Thermal Processing of Semiconductors, 2003, pp. 17–33
Ahsan, et al., RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65 nm technology, in IEEE Symposium on VLSI Technology, 2006, pp. 170–171
P. Hazucha, et al., Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 μm to 90-nm generation, in IEEE International Electron Devices Meeting, 2003, pp. 21.5.1–21.5.4
P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, L. Alvisi, Modelling the effect of technology trends on the soft error rate of combinational logic, in Proceedings of the International Conference on Dependable Systems and Networks, 2002, pp. 389–398
Z. Quming, K. Mohanram, Gate sizing to radiation harden combinational logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25, 155–166 (2006)
R.C. Baumann, Soft errors in advanced semiconductor devices-part I: the three radiation sources. IEEE Trans. Device Mater. Reliab. 1, 17–22 (2001)
K.A. Bowman et al., A 45 nm resilient microprocessor core for dynamic variation tolerance. IEEE J. Solid-State Circuits 46(1), 194–208 (2011)
Y.-B. Kim, K.K. Kim, J. Doyle, A CMOS low power fully digital adaptive power delivery system based on finite state machine control, in Proceedings of IEEE International Symposium Circuits and Systems, 2007, pp. 1149–1152
J. Tschanz, et al., Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging, in Digest of Technical Papers IEEE International Solid-State Circuits Conference, 2007, pp. 292–604
S.-C. Lin, K. Banerjee, A design-specific and thermally-aware methodology for trading-off power and performance in leakage-dominant CMOS technologies. IEEE Trans. Very Large Scale Integr. Syst. 16(11), 1488–1498 (2008)
K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, D. Ha, D. Ham, Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoring, in Digest of Technical Papers IEEE Solid-State Circuits Conference, 2009, pp. 68–69
S. Dighe et al., Within-die variation-aware dynamic-voltagefrequency-scaling with optimal core allocation and thread hopping for the 80-core TeraFLOPS processor. IEEE J. Solid-State Circuits 46(1), 184–193 (2011)
T. Fischer, J. Desai, B. Doyle, S. Naffziger, B. Patella, A 90 nm variable frequency clock system for a power-managed itanium architecture processor. IEEE J. Solid-State Circuits 41(1), 218–228 (2006)
N. Drego, A. Chandrakasan, D. Boning, D. Shah, Reduction of variation-induced energy overhead in multi-core processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6), 891–904 (2011)
P.R. Kinget, Device mismatch and tradeoffs in the design of analog circuits. IEEE J. Solid-State Circuits 40(6), 1212–1224 (2005)
K.K. Kim, W. Wang, K. Choi, On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits. IEEE Trans. Circuits Syst. II: Express Briefs 57(10), 798–802 (2010)
R. Rao, K.A. Jenkins, J–.J. Kim, A local random variability detector with complete digital on chip measurement circuitry. IEEE J. Solid-State Circuits 44(9), 2616–2623 (2009)
N. Mehta, B. Amrutur, Dynamic supply and threshold voltage scaling for CMOS digital circuits using in situ power monitor. IEEE Trans. Very Large Scale Integr. Syst. 20(5), 892–901 (2012)
M. Mostafa, M. Anis, M. Elmasry, On-chip process variations compensation using an analog adaptive body bias (A-ABB). IEEE Trans. Very Large Scale Integr. Syst. 20(4), 770–774 (2012)
R. McGowen, C.A. Poirier, C. Bostak, J. Ignowski, M. Millican, W.H. Parks, S. Naffziger, Power and temperature control on a 90 nm itanium family processor. IEEE J. Solid-State Circuits 41(1), 229–237 (2006)
A.P. van der Wel, E.A.M. Klumperink, L.K.J. Vandamme, B. Nauta, Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise. IEEE Trans. Electron Devices 50(5), 1378–1384 (2003)
K. Okada, S. Kousai (eds.), Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio (Springer Verlag GmbH, New York, 2011)
M. Verhelst, B. Murmann, Area scaling analysis of CMOS ADCs. IEEE Electron. Lett. 48(6), 314–315 (2012)
M. Pelgrom, A. Duinmaijer, A. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989)
B. Calhoun, A. Wang, A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits 40(9), 1778–1786 (2005)
P. Macken, M. Degrauwe, M.V. Paemel, H. Oguey, A voltage reduction technique for digital systems, in Digest of Techical Papers IEEE International Solid-State Circuits Conference, 1990, pp. 238–239
K.J. Kuhn, Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS, in IEEE International Electronic Devices Meeting, 2007, pp. 471–474
B. Zhai, S. Hanson, D. Blaauw, D. Sylvester, Analysis and mitigation of variability in subthreshold design, in IEEE International Symposium on Low Power Electronic Design, 2005, pp. 20–25
A. Wang, A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40(1), 310–319 (2005)
J. Chen, L.T. Clark, Y. Cao, Robust design of high fan-in/out subthreshold circuits, in IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2005, pp. 405–410
J. Chen, L.T. Clark, T.-H. Che, An ultra-low-power memory with a subthreshold power supply voltage. IEEE J. Solid-State Circuits 41(10), 2344–2353 (2006)
J. Kwong, Y.K. Ramadass, N. Verma, A.P. Chandrakasan, A 65 nm Sub-Vt microcontroller with integrated SRAM and switched capacitor dc–dc converter. IEEE J. Solid-State Circuits 44(1), 115–126 (2009)
Y. Cao, L.T. Clark, Mapping statistical process variations toward circuit performance variability: An analytical modeling approach, in IEEE Design Automation Conference, 2005, pp. 658–663
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2014 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Zjajo, A. (2014). Introduction. In: Stochastic Process Variation in Deep-Submicron CMOS. Springer Series in Advanced Microelectronics, vol 48. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-7781-1_1
Download citation
DOI: https://doi.org/10.1007/978-94-007-7781-1_1
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-7780-4
Online ISBN: 978-94-007-7781-1
eBook Packages: EngineeringEngineering (R0)