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Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture

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IAENG Transactions on Engineering Technologies

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 247))

Abstract

Advanced integration technologies enable the construction of Network-on-Chip (NoC) from two dimensions to three dimensions. Studies have shown that 3D NoCs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. This paper presents a defect tolerance technique for recovering permanent routers failure through an efficient and effective use of redundancy. This technique is ideally suited for three and even two dimensional network-on-chip (NoC). This fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented. Simulation results demonstrate significant reliability and yield improvement. Although the hardware overhead of the 3D (2D)-proposed methodology compare with traditional mesh is approximately 15 % (12 %), it improves the average response time of system up to 31 % (23 %).

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Author information

Authors and Affiliations

  1. Science and Research Branch, Islamic Azad University, Tehran, Iran

    Farnoosh Hosseinzadeh & Majid Janidarmian

  2. University of California, Irvine, USA

    Nader Bagherzadeh

  3. Iran Telecommunication Research Center, Tehran, Iran

    Ahmad Khademzadeh

Authors
  1. Farnoosh Hosseinzadeh
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  2. Nader Bagherzadeh
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  3. Ahmad Khademzadeh
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  4. Majid Janidarmian
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Corresponding author

Correspondence to Farnoosh Hosseinzadeh .

Editor information

Editors and Affiliations

  1. Computer & Communication Dean of Engineering College, Catholic University of DaeGu Engineering College, DaeGu, Korea, Republic of (South Korea)

    Haeng Kon Kim

  2. Unit 1, 1/F, International Association of Engineers, Hong Kong, Hong Kong SAR

    Sio-Iong Ao

  3. College of Engineering, California State Polytechnic University, Pomona, California, USA

    Mahyar A. Amouzegar

  4. Abt. Linguistische Datenverarbeitung, Universität Trier Inst.Computerlinguistik, Trier, Germany

    Burghard B. Rieger

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Hosseinzadeh, F., Bagherzadeh, N., Khademzadeh, A., Janidarmian, M. (2014). Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture. In: Kim, H., Ao, SI., Amouzegar, M., Rieger, B. (eds) IAENG Transactions on Engineering Technologies. Lecture Notes in Electrical Engineering, vol 247. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6818-5_26

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  • DOI: https://doi.org/10.1007/978-94-007-6818-5_26

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  • Online ISBN: 978-94-007-6818-5

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