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Fundamentals of Non-Volatile Memories

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Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 40))

Abstract

The subject of this chapter is to introduce the fundamentals of non-volatile memories. An overview about electron and non-electron based cells is given followed by a cell assessment for high density non-volatile memories. The link between memory cell and memory array performance parameters is introduced and in depth analysed for NAND and NOR array architectures. The design specific aspects of sensing and program and erase algorithm techniques are introduced for floating gate and charge trapping cell based flash memories.

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Notes

  1. 1.

    NROM\(^\mathrm{TM}\) invented by Saifun Technlogies, MirrorBit\(^\mathrm{TM}\) used by AMD and Spansion, TwinFlash\(^{\circledR }\) used by Infineon Technologies Flash GmbH.

References

  1. K. Kahng, S. Sze, A floating gate and its application to memory devices. IEEE Trans. Electron Dev. Bd. 46, 629 (1967)

    Article  Google Scholar 

  2. F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S. Tanaka, A new Flash E2PROM cell using triple polysilicon technology, in IEEE IEDM Techn Digest, pp. 464–467, Washington, 1984.

    Google Scholar 

  3. M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, K. Wojciechowski, A multilevel-cell 32Mb flash memory, in ISSCC Digest of Technical Papers, pp. 132–133, San Francisco, 1995.

    Google Scholar 

  4. K.-D. Suh, B.-H. Suh, Y.-H. Um, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H. Choi, J.-R. Kim, H.-K. Lim, A 3.3V 32Mb NAND flash memory with incremental step pulse programming scheme, in ISSCC Digest of Technical Papers, pp. 128–129, San Francisco, 1995.

    Google Scholar 

  5. P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, T.-J. King, FinFET SONOS flash memory for embedded applications, in IEDM Technical Digest, pp. 609–612, Washington, 2003.

    Google Scholar 

  6. M. Stadele, R. Luyken, M. Roosz, M. Specht, W. Rosner, L. Dreeskornfeld, J. Hartwich, F. Hofmann, J. Kretz, E. Landgraf, L. Risch, A comprehensive study of corner effects in tri-gate transistors, in Solid-State Device Research conference, Procedings ESSDERC, pp. 165–168, 2004.

    Google Scholar 

  7. G.E. Moore, Cramming more components onto integrated circuits. Electron. Bd. 38(8), 114–117 (1965)

    Google Scholar 

  8. S. Mukherjee, T. Chang, R. Pang, M. Knecht, D. Hu, A single transistor EEPROM cell and its implementation in a 512 K CMOS EEPROM, in IEDM Technical Digest, pp. 616–619, Washington, 1985.

    Google Scholar 

  9. J. Lee, V. Dham, Design considerations for scaling FLOTOX E2PROM cell, in IEDM Technical Digest, pp. 589–592, Washington, 1983.

    Google Scholar 

  10. J.E. Brewer, G. Manzur, Nonvolatile Memory Technologies with Emphasis on Flash: a Comprehensive Guide to Understanding and Using NVM Devices, Auflage, 1st edn. (Wiley, Hoboken, 2008)

    Google Scholar 

  11. R.J. Baker, in Memory circuits-pheripheral circuits. CMOS Circuit Design, Layout, and Simulation (IEEE Press, Wiley Interscience, Piscataway, 2005), pp. 448–456.

    Google Scholar 

  12. B. Prince, Semiconductor Memories: A Handbook of Design, Manufacture, and Application, 2nd edn. (Wiley, New York, 1991)

    Google Scholar 

  13. E. Snow, Fowler-Nordheim tunneling in SiO2 films. Solid State Commun. 5, 813–815 (1967)

    Article  ADS  Google Scholar 

  14. C. Friederich, Multi level programming scheme with reduced cross coupling, in Control of harmful effects in program operation of NAND flash (Aachen, Shaker, 2011), pp. 62–66

    Google Scholar 

  15. R. Bez, D. Cantarelli und S. S. The channel hot electron programming of a floating gate MOSFET: an analytical study, in 12th Nonvolatile Semiconductor Memory Workshop, Monterey, California, 1992.

    Google Scholar 

  16. M.-S. Liang, Memory cell having hot-hole injection erase mode, USA Patent 4472491, 1985.

    Google Scholar 

  17. T. Chan, J. Chen, P. Ko, C. Hu, The impact of gate-induced drain leakage current on MOSFET scaling, in IEDM Technical Digist, pp. 718–721, Washington, 1987.

    Google Scholar 

  18. P. Cappelletti, C. Golla, P. Olivio, E. Zanoni, Physical aspects of cell operation and reliability, in Flash Memories (Kluwer-Academic Publisher, Dordrecht, 1999), p. 171

    Google Scholar 

  19. S. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981)

    Google Scholar 

  20. H. Wegener, A. Lincoln, H. Pao, M. O’Connell, R. Oleksiak, H. Lawrence, The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device, in IEDM, Technical Digest, vol. 13, pp. 70–70, Washington, 1967.

    Google Scholar 

  21. P. Chen, Threshold-alterable Si-gate MOS devices, transactions on electron devices. IEEE 24(5), 584–586 (1977)

    Google Scholar 

  22. F. MIENO, SANOS Memory Cell Structure, United States Patent US 2010/0001353 A1, 07 Jan 2010.

    Google Scholar 

  23. Y. Park, J. Choi, C. Kang, C. Lee, Y. Shin, B. Choi, J. Kim, S. Jeon, J. Sel, J. Park, K. Choi, T. Yoo, J. Sim, K. Kim, Highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 \(\upmu \)m2 Cell size using TANOS(Si-Oxide- Al2O3-TaN) cell technology, in IEDM, Technical Digest, pp. 1–4, Washington, 2006.

    Google Scholar 

  24. C. Kang, J. Choi, J. Sim, C. Lee, Y. Shin, J. Park, J. Sel, S. Jeon, Y. Park, K. Kim, Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory, in IEEE Reliability physics symposium, proceedings. 45th, pp. 167–170, Phoenix, AZ, 2007.

    Google Scholar 

  25. C. Friederich, M. Specht, T. Lutz, F. Hofinann, L. Dreeskornfeld, W. Weber, J. Kretz, T. Melde, W. Rosner, E. Landgraf, J. Hartwich, M. Stadele, L. Risch, D. Richter, Multi-level p+ tri-gate SONOS NAND string arrays, in IEDM Technical Digest, pp. 1–4, Washington, 2006.

    Google Scholar 

  26. M. Specht, U. Dorda, L. Dreeskornfeld, J. Kretz, F. Hofinann, M. Stadele, R. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, R. Kommling, L. Risch, 20 nm tri-gate SONOS memory cells with multi-level operation, in IEDM Technical Digest, pp. 1083–1085, Washington, 2004.

    Google Scholar 

  27. Y.-H. Shih, H.-T. Lue, K.-Y. Hsieh, R. Liu, C.-Y. Lu, A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance, in IEDM Technical Digest, pp. 881–884, Washington, 13–15 Dec 2004.

    Google Scholar 

  28. E. Stein, V. Kamienski, M. Isler, T. Mikolajick, C. Ludwig, N. Schulze, N. Nagel, S. Riedel, J. Wilier, K.-H. Kusters, An Overview on Twin Flash Technology, in Non-Volatile Memory Technology Symposium, Dallas, 2005.

    Google Scholar 

  29. A. Shappir, E. Lusky, G. Cohen, B. Eitan, NROM Window Sensing for 2 and 4-bits per cell Products, in NVSMWS (Monterey, CA, 2006)

    Google Scholar 

  30. M. Janai, Threshold voltage fluctuations in localized charge-trapping nonvolatile memory devices. IEEE Trans. Electron Dev. 59, 596–601 (2012)

    Article  ADS  Google Scholar 

  31. J.-G. Yun, I.H. Park, S. Cho, J.H. Lee, D.-H. Kim, G.S. Lee, Y. Kim, J.D. Lee, B.-G. Par, A 2-bit recessed channel nonvolatile memory device with a lifted charge-trapping node. IEEE Trans. Nanotechnol. 8, 111–115 (2009)

    Article  ADS  Google Scholar 

  32. L. Hai, M. Takahashi, S. Sakai, Downsizing of ferroelectric-gate-field-effect-transistors for ferroelectric-NAND flash memory, in 3rd IEEE International Memory Workshop (IMW), pp. 1–4, Monterey, CA, June 2011.

    Google Scholar 

  33. J. Müller, E. Yurchuk, T. Schlosser, J. Paul, R. Hoffmann, S. Muller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kucher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schroder, T. Mikolajick, Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG,“ in Symposium on VLSI Technology (VLSIT), 2012, Honolulu, 2012.

    Google Scholar 

  34. M. Durlam, P.J. Naji, A. Omair, M. DeHerrera, J. Calder, J.M. Slaughter, B.N. Engel, A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects. IEEE J. Solid-State Circuits 38, 769–773 (2003)

    Article  Google Scholar 

  35. Y. Huai, Y. Zhou, I. Tudosa, R. Malmhall, R. Ranjan, J. Zhang, Progress and outlook for STT-MRAM, in International Conference on Computer-Aided Design (ICCAD), IEEE/ACM, pp. 235, San Jose, 2011.

    Google Scholar 

  36. S. Lai, Current status of the phase change memory and its future, in IEDM Technical Digest, pp. 10.1.1-10.1.4, Washington, 2003.

    Google Scholar 

  37. K. Byeungchul, S. Yoonjong, A. Sujin, K. Younseon, J. Hoon, A. Dongho, N. Seokwoo, J. Gitae, C. Chilhee, Current status and future prospect of Phase Change Memory, in IEEE 9th International Conference on ASIC (ASICON), 2011, pp. 279–282, Xiamen, 2011.

    Google Scholar 

  38. F. Bedeschi, R. Fackenthal, C. Resta, E. Donze, M. Jagasivamani, E. Buda, F. Pellizzer, D. Chow, A. Cabrini, G. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi, G. Casagrande, A Bipolar-selected Phase Change Memory featuring Multi-Level Cell Storage. IEEE J. Solid-State Circuits Bd. 1(1, Jan 2001), 217–227 (2009).

    Google Scholar 

  39. M. Specht, R. Kommling, F. Hofmann, V. Klandzievski, L. Dreeskornfeld, W. Weber, J. Kretz, E. Landgraf, T. Schulz, J. Hartwich, W. Rosner, M. Stadele, R. Luyken, H. Reisinger, A. Graham, E. Hartmann, L. Risch, Novel dual bit tri-gate charge trapping memory devices. IEEE Electron Device Lett. 25, 810–812 (2004)

    Article  ADS  Google Scholar 

  40. A. Fazio, Non-volatile memory technology: present and future trends, in ISSCC, Tutorial F1, San Francisco, 2007.

    Google Scholar 

  41. J. Javanifard, T. Tanadi, H. Giduturi, K. Loe, R. Melcher, S. Khabiri, N. Hendrickson, A. Proescholdt, D. Ward, M. Taylor, A 45 nm Self-Aligned-Contact Process 1 Gb NOR Flash with 5 MB/s Program Speed, in ISSCC Digest of Technical Papers, pp. 424–426, San Francisco, 2008.

    Google Scholar 

  42. B. Le, M. Achter, C. G. Chng, X. Guo, L. Cleveland, P.-L. Chen, M. Van Buskirk, R. Dutton, Virtual-ground sensing techniqus for a 49ns/200MHz access time 1.8V 256Mb 2-bit-per-cell flash memory. IEEE J. Solid-State Circuits 2014–2023 (2004).

    Google Scholar 

  43. R. Koval, V. Bhachawat, C. Chang, M. Hajra, D. Kencke, Y. Kim, C. Kuo, T. Parent, M. Wei, B. Woo, A. Fazio, Flash ETOX(TM) virtual ground architecture: a future scaling directions, in VLSI Technology, Digest of Technical Papers, pp. 204–205, Kyoto, 2005.

    Google Scholar 

  44. C. Yeh, W. Tsai, T. Lu, Y. Liao, N. Zous, H. Chen, T. Wang, W. Ting, J. Ku, C.-Y. Lu, Reliability and device scaling challenges of trapping charge flash Mmemories, in Proceedings of 11th IPFA, pp. 247–250, Taiwan, 2004.

    Google Scholar 

  45. N. Ito, Y. Yamauchi, N. Ueda, K. Yamamoto, Y. Sugita, T. Mineyama, A. Ishihama, K. Moritani, A novel program and read architecture for contact-less virtual ground NOR flash memory for high density Application, in Symposium on VLSI Circuits Digist of Technical Paper, pp. 116–117, Honolulu, 2006.

    Google Scholar 

  46. K.-R. Han, H.-A.-R. Jung, J.-H.L. Lee, Band-to-Band Hot-hole Erase Characterisitcs of 2-Bit/cell NOR type SONOS flash memory cell with spacer-type storage node on recessed channel structure. Japan. J. Appl. Phys. 33, 798–800 (2007)

    Article  Google Scholar 

  47. Y. Sofer, NROM Memory Design, in ISSCC 2007-Non-Volatile Memory Circuit Design and Technology, San Francisco, 2007.

    Google Scholar 

  48. M. Momodomi, Y. Itoh, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T. Tanaka, S. Aritome, T. Endoh, K. Ohuchi, F. Masuoka, An experimenatal 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid-State Circuits 24, 1238–1243 (1989)

    Article  Google Scholar 

  49. D. Richter, Vorlesung Halbleiter Bauelemente–Nichtflüchtige Speicher Titel: NVM Shrink Roadmap 3–4bit/cell NAND–Key Performance Indicator, München: TUM (Lehrstuhl für Technische Elektronik, Fakultät für Elektro- und Informationstechnik, 2008)

    Google Scholar 

  50. T.-S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H. Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Yi, H.-K. Lim, A 117-mm2 3,3V only 128 Mb multilevel NAND flash memory for mass storage application. IEEE J. Solid-State Circuits 31, 1575–1583 (1996)

    Article  Google Scholar 

  51. T. Tanzawa, T. Tanaka, K. Takeuchi, H. Nakamura, Circuit techniques for a 1,8V only NAND flash memory. IEEE J. Solid-State Circuits 37, 84–89 (2002)

    Article  Google Scholar 

  52. N. Fujita, N. Tokiwa, Y. Shindo, T. Edahiro, T. Kamei, H. Nasu, M. Iwai, K. Kato, Y. Fukuda, N. Kanagawa, N. Abiko, M. Matsumoto, T. Himeno, T. Hashimoto, Y.-C. Liu, H. Chibvongodze, T. Hori, M. Sakai, A 113mm2 32Gb 3b/cell NAND flash memory, in ISSCC-Digest of Technical Papers, pp. 242–233, San Francisco, 2009.

    Google Scholar 

  53. E. Harari, NAND at center stage, in Flash Memory Summit, Santa Clara, 8 August 2007.

    Google Scholar 

  54. M. Bauer, NOR flash memory design-non-volatile memories technology and design, in ISSCC 2004 Memory Circuit Design Forum, San Francisico, 2004.

    Google Scholar 

  55. K. Tedrow, NOR flash memory design, in ISSCC 2007-Non-Volatile Memory Design Forum, San Francisco, 2007.

    Google Scholar 

  56. C. Friederich, in Program and erase of NAND memory arrays, eds. by R. Micheloni, L. Crippa, A. Marelli, Inside NAND Flash Memories (Springer, Dordrecht, 2010), pp. 75–76.

    Google Scholar 

  57. T. Tanaka, A quick Intelligent Page-Programming Architecture and a shileded bitline sensing method for 3 V only NAND Flash Memory. IEEE J. Solid-State Circuits 29, 1366–1373 (1994)

    Article  Google Scholar 

  58. F. Koichi, Y. Watanabe, E. Makino, K. Kawakami, J. Sato, T. Takagiwa, N. Kanagawa, H. Shiga, N. Tokiwa, Y. Shindo, T. Edahiro, T. Ogawa, M. Iwai, O. Nagao, J. Musha, T. Minamoto, K. Yanagidaira, Y. Suzuki, D. Nakamura, Y. Hosomura, A 151mm2 64Gb MLC NAND flash memory in 24 nm CMOS technology, in ISSCC, Digest of Technical Papers, pp. 198–199, San Francisco, 2011.

    Google Scholar 

  59. M. Bauer, Multi-level Cell Design for flash memory, in ISCC 2006 Tutorial T5: MLC Design for Flash Memory ( Feb, San Francisco, 2006).

    Google Scholar 

  60. J. Lee, S.-S. Lee, O.-S. Kwon, K.-H. Lee, D.-S. Byeon, I.-Y. Kim, K.-H. Lee, Y.-H. Lim, B.-S. Choi, J.-S. Lee, W.-C. Shin, J.-H. Choi, K.-D. Suh, A 90-nm CMOS 1.8V 2Gb NAND flash memory for Mass storage application. IEEE J Solid-State Circuits 38(11), 1934–1942 2003 (Bde. %1 von %2).

    Google Scholar 

  61. T. Tanaka, NAND flash design, in ISSCC, Non-Volatile Memory Circuit and Technology Tutorial F1, San Francisco, 2007.

    Google Scholar 

  62. T. Hara, K. Fukuda, K. Kanazawa, N. Shibata, K. Hosono, H. Maejima, M. Nakagawa, T. Abe, M. Kojima, M. Fujiu, Y. Takeuchi, K. Amemiya, M. Morooka, T. Kamei, H. Nasu, C.-M. Wang, K. Sakurai, N. Tokiwa, H. Waki, T. Maruyama, S. Yoshikawa, A 146-mm2 8-Gb Multi-level NAND flash memory with 70-nm CMOS technology. IEEE J. Solid-State Circuits 41, 161–169 (2006)

    Article  Google Scholar 

  63. R. Cernea, D. Lee, M. Mofidi, E. Chang, W. Y. Chien, L. Goh, Y. Fong, J. Yuan, G. Samachisa, D. Guterman, S. Mehrotra, K. Sato, H. Onishi, K. Ueda, F. Noro, K. Mijamoto, M. Morita, K. Umeda, K. Kubo, A 34Mb 3.3V Serial Flash EEPROM for solid-state disk applications, in ISSCC Digest of Tech Papers, pp. 126–127, San Francisco, 1995.

    Google Scholar 

  64. R. Cernea, o. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T.-Y. Tseng, K. Nguyen, J. Li, J. Hu, J. Park, C. Hsu, F. Zhang, T. Kamei, H. Nasu, P. Kliza, K. Htoo, J. Lutze, und Y. Dong, A 34MB/s-program-throughput 16Gb MLC NAND with all-bitline architecture in 56nm, in ISSCC Digest of technical Papers, pp. 420–424, San Francisco, 2008.

    Google Scholar 

  65. J.F. Dickson, On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique. IEEE J. Solid-State Circuits 11, 374–378 (1976)

    Article  Google Scholar 

  66. C.-C. Wang, J.-C. Wu, Efficiency improvement in charge pump circuits. IEEE J. Solid-State Circuits 32(6), 852–860 (1998)

    Article  Google Scholar 

  67. T. Tanzawa, T. Tanaka, A stable programming pulse generator for single power supply flash memories. IEEE J. Solid-State Circuits 32(6), 845–851 (1997)

    Article  Google Scholar 

  68. F. Pan, T. Samaddar, Charge pump circuit design, 1st edn. (Mcgraw-Hill Professional, New York, 2006).

    Google Scholar 

  69. K. Kim, G. Jeong, Memory technologies in the nano-era: challenges and opportunities, in ISSCC Digest of Technical Papers, pp. 576–578, San Francsico, 2005.

    Google Scholar 

  70. K. Kim, J. Coi, Future outlook of NAND flash technology for 40 nm node and beyond, in IEEE NVSMW, pp. 9–11, Monterey, CA, 2006.

    Google Scholar 

  71. T. Tanaka, A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-Only NAND flash memory. IEEE JSSC Bd. 29(11), 1366 (1994)

    Google Scholar 

  72. C. Kim, J. Ryu, T. Lee, H. Kim, J. Lim, J. Jeong, S. Seo, H. Jeon, B. Kim, I. Lee, D. Lee, P. Kwak, S. Cho, Y. Yim, C. Cho, W. Jeong, K. Park, J.-M. Han, D. Song, K. Kyung, A 21 nm High Performance 64 Gb MLC NAND flash memory With 400 MB/s asynchronous toggle DDR interface. IEEE J. Solid-State Circuits 47, 981–989 (2012)

    Article  Google Scholar 

  73. J. Han, B. Lee, J. Han, W. Kwon, C. Chang, S. Sim, C. Park, K. Kim, A critical failure source in 65nm-MLC NOR flash memory incorporating co-salicidation process, in Integrated Reliability Workshop Final Report, pp. 80–82, South Lake Tahoe, CA, Sep 2006.

    Google Scholar 

  74. A. Bergemont, M.-H. Chi, H. Haggag, Low voltage NVGTM: a new high performance 3 V/5 V flash technology for portable computing and telecommunications applications. IEEE Trans. Electron Devices 43(9), 1510–1517 (1996)

    Article  ADS  Google Scholar 

  75. N. Ito, Y. Yamauchi, N. Ueda, K. Yamamoto, Y. Sugita, T. Mineyama, A. Ishihama, K. Moritani, A novel program and read architecture for contact-less virtual ground NOR flash memory for high density application, in Symposium on VLSI Circuits, Digest of Technical Papers, pp. 116–117, Honolul, HI, 2006.

    Google Scholar 

  76. N. Zous, M. Lee, W. Tsai, A. Kuo, L. Huang, T. Lu, C. Liu, T. Wang, W. Lu, W. Ting, J. Ku, C.-Y. Lu, Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology. IEEE Electron Device Lett. 25, 649–651 (2004)

    Article  ADS  Google Scholar 

  77. Y. Roizin, Extending endurance of NROM memories to over 1 million program/erase cycles, in Proceedings of 21st Non-Volatile Semiconductor Memory, Workshop, pp. 74–75, Feb 2006.

    Google Scholar 

  78. T. Kuo, N. Yang, N. Leong, E. Wang, F. Lai, A. Lee, H. Chen, S. Chandra, Y. Wu, T. Akaogi, A. Melik-Martirosian, A. Pourkeramati, J. Thomas, M. VanBuskirk, Design of 90nm 1Gb ORNAND(TM) flash memory with mirrorBit(TM) technology, in Symposium on VLSI Circuits Digest of Technical Papers, pp. 114–115, Honolulu, HI, 2006.

    Google Scholar 

  79. N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N. Motohashi, A 70 nm 16 Gb 16-level-cell NAND flash memory. IEEE J. Solid-State Circuits 43, 929–937 (April 2008)

    Article  Google Scholar 

  80. Y. Li, S. Lee, Y. Fong, F. Pan, T.-C. Kuo, P. J., T. Samaddar, H. T. Nguyen, M. Mui, K. Htoo, T. Kamei, M. Higashitani, E. Yero, G. Kwon, P. Kliza, J. Wan, T. Kaneko, H. Maejima, H. Shiga, M. Hamada und N. Fujita, A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate. IEEE J. Solid-State Circuits 44(1), 195–207 (2009) (Bd. 44).

    Google Scholar 

  81. B.T. Park, J.H. Song, E.S. Cho, S.W. Hong, J.Y. Kim, Y.J. Choi, Y.S. Kim, S.J. Lee, C.K. Lee, D.W. Kang, D.J. Lee, B.T. Kim, Y.J. Choi, W.K. Lee, J.-H. Choi, K.-D. Su, 32nm 3-bit 32Gb NAND flash memory with DPT (double patterning technology) process for mass production, in VLSI Technology (VLSIT), pp. 125–126, 2010.

    Google Scholar 

  82. N. Giovanni, A 3bit/Cell 32Gb NAND Flash Memory at 34nm with 6MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput Increase up to 13MB/s, San Francisco, 2010.

    Google Scholar 

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Richter, D. (2014). Fundamentals of Non-Volatile Memories. In: Flash Memories. Springer Series in Advanced Microelectronics, vol 40. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6082-0_2

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