Abstract
Consider the case of a 1 megabit (Mb) SRAM array, which has 1 million “identical” instances of an SRAM cell. These instances are designed to be identical, but due to manufacturing variations, they usually differ. Suppose we desire a chip yield of 99%; that is, no more that one chip per 100 should fail. This means that on average, not more than (approx.) one per 100×1 million SRAM cells; that is 10 per billion, should fail. This translates to a required circuit yield of 99.999999%, or a maximum failure rate of 0.01 ppm for the SRAM cell. This failure probability is the same as for a 5.6σ point on the standard normal distribution. If we want to estimate the yield of such an SRAM cell in the design phase, a standard Monte Carlo approach would require at least 100 million SPICE simulations on average to obtain just one failing sample point! Even then, the estimate of the yield or failure probability will be suspect because of the lack of statistical confidence, the estimate being computed using only one failing example. Such a large number of simulation is utterly intractable. This example clearly illustrates the widespread problem with designing robust memories in the presence of process variations: we need to simulate rare or extreme events and estimate the statistics of these rare events. The problem of simulating and modeling rare events stands for any circuit that has a large number of identical replications on the same chip, as in DRAM arrays and non-volatile memories. We term such circuits as high replication circuits (HRCs).
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© 2009 Springer Science + Business Media B.V.
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Singhee, A., Rutenbar, R.A. (2009). Statistical Blockade: Estimating Rare Event Statistics. In: Novel Algorithms for Fast Statistical Analysis of Scaled Circuits. Lecture Notes in Electrical Engineering, vol 46. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3100-6_3
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DOI: https://doi.org/10.1007/978-90-481-3100-6_3
Publisher Name: Springer, Dordrecht
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