Skip to main content
SpringerLink
Log in

Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra

  • Conference paper
  • First Online:
Computational Advancement in Communication Circuits and Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 335))

Abstract

Digital signal processing (DSP) operations are very important part of engineering as well as medical discipline. Designing of DSP operations have many approaches. For the designing of DSP operations, multiplication plays a important role to perform signal processing operations such as convolution and correlation. The aim of this paper is to design a multiplier circuit based on Vedic sutras and method for DSP operations based on ancient Vedic mathematics is contemplated. In this paper, we have given the design up to multipliers based on Vedic multiplication sutra ‘Urdhva-Tiryakbhyam’ the design of 4 × 4 has been sketched in DSCH2 and all the outputs have been given. The layout of those circuits has also been generated by Microwind. The internal circuit diagram of all the blocks has been explained. The noise power have been calculated by T-Spice-13 in 45 nm Technology. This algorithm is implemented in MATLAB and also compared with the inbuilt functions in MATLAB.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R. Saligram, T.R. Rakshith, Optimized reversible Vedic multipliers for high speed low power operations, in Proceedings of IEEE Conference on Information and Communication Technologies (ICT 2013) (2013)

    Google Scholar 

  2. H.D. Tiwari, G. Gankhuyag, C.M. Kim, Y.B. Cho, Multiplier design based on ancient Indian Vedic mathematics, in IEEE International SoC Design Conference, 978-1-4244-2599-0/08/$25.00 ©2008

    Google Scholar 

  3. A. Kanhe, S.K. Das, A.K. Singh, Design and implementation of floating point multiplier based on Vedic multiplication technique, in International Conference on Communication, Information & Computing Technology (ICCICT), Mumbai, India, 19–20 Oct 2012

    Google Scholar 

  4. P. Mehta, D. Gawali, Conventional versus Vedic mathematical method for hardware implementation of a multiplier, in International Conference on Advances in Computing, Control, and Telecommunication Technologies

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Radio Physics and Electronics, Rajabazar Science College, Kolkata, India

    Supriyo Srimani

  2. Electronics and Telecommunication Department, Narula Institute of Technology, Kolkata, India

    Diptendu Kumar Kundu

  3. ECE Department, Narula Institute of Technology, Kolkata, India

    Saradindu Panda

  4. ECE Department, National Institute of Technology, Durgapur, India

    B. Maji

Authors
  1. Supriyo Srimani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Diptendu Kumar Kundu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Saradindu Panda
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. B. Maji
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Supriyo Srimani .

Editor information

Editors and Affiliations

  1. School of Electronics & Computer Science, University of Southampton, Southampton, United Kingdom

    Koushik Maharatna

  2. Design & Growth, Institute of Materials Research & Engg, Singapore, Singapore

    Goutam Kumar Dalapati

  3. Electronics and Telecommunication Engg, Jadavpur University, Kolkata, West Bengal, India

    P K Banerjee

  4. Electronics and Electrical Communication, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India

    Amiya Kumar Mallick

  5. Centre for Millimeter Wave Semiconductor Devices and Systems, Defence Research and Development Org., Kolkata, West Bengal, India

    Moumita Mukherjee

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer India

About this paper

Cite this paper

Srimani, S., Kundu, D.K., Panda, S., Maji, B. (2015). Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra. In: Maharatna, K., Dalapati, G., Banerjee, P., Mallick, A., Mukherjee, M. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 335. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2274-3_49

Download citation

  • DOI: https://doi.org/10.1007/978-81-322-2274-3_49

  • Published:

  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-2273-6

  • Online ISBN: 978-81-322-2274-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation