Skip to main content

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams

  • Conference paper
Reversible Computation (RC 2012)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 7581))

Included in the following conference series:

Abstract

For the validation and verification of quantum circuits mainly techniques based on simulation are applied. Although lots of effort has been put into the improvement of these techniques, ensuring the correctness still requires an exhaustive consideration of all input vectors. As a result, these techniques are particularly insufficient to prove a circuit to be error free.

As an alternative, we present a symbolic formal verification method that is based on Quantum Multiple-Valued Decision Diagrams (QMDDs), a data-structure allowing for a compact representation of quantum circuits. As a result, using QMDDs it is possible to check the correctness of a circuit without exhaustively considering all input patterns.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 49.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, New York (2000)

    MATH  Google Scholar 

  2. Hung, W.N.N., Song, X., Yang, G., Yang, J., Perkowski, M.A.: Quantum logic synthesis by symbolic reachability analysis. In: Malik, S., Fix, L., Kahng, A.B. (eds.) Design Automation Conference, pp. 838–841. ACM (June 2004)

    Google Scholar 

  3. Shende, V.V., Bullock, S.S., Markov, I.L.: Synthesis of quantum logic circuits. In: Tang, T. (ed.) Asia and South Pacific Design Automation Conference, pp. 272–275. ACM Press (January 2005)

    Google Scholar 

  4. Große, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares. In: Int’l Symp. on Multiple-Valued Logic, pp. 214–219 (May 2008)

    Google Scholar 

  5. Maslov, D., Dueck, G.W., Miller, D.M., Negrevergne, C.: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD 27(3), 436–444 (2008)

    Google Scholar 

  6. Soeken, M., Wille, R., Dueck, G.W., Drechsler, R.: Window optimization of reversible and quantum circuits. In: Int’l Symp. on Design and Diagnostics of Electronic Circuits and Systems, pp. 341–345 (April 2010)

    Google Scholar 

  7. Yuan, J., Shultz, K., Pixley, C., Miller, H., Aziz, A.: Modeling design constraints and biasing in simulation using BDDs. In: Int’l Conf. on Computer-Aided Design, pp. 584–590 (November 1999)

    Google Scholar 

  8. Bergeron, J.: Writing Testbenches Using SystemVerilog. Springer (2006)

    Google Scholar 

  9. Yuan, J., Pixley, C., Aziz, A.: Constraint-Based Verification. Springer (January 2006)

    Google Scholar 

  10. Wille, R., Große, D., Haedicke, F., Drechsler, R.: SMT-based Stimuli Generation in the SystemC Verification Library. In: Forum on Specification & Design Languages (September 2009)

    Google Scholar 

  11. Brand, D.: Verification of large synthesized designs. In: Lightner, M.R., Jess, J.A.G. (eds.) Int’l Conf. on Computer-Aided Design, pp. 534–537. IEEE Computer Society (1993)

    Google Scholar 

  12. Disch, S., Scholl, C.: Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets. In: Asia and South Pacific Design Automation Conference, pp. 938–943 (2007)

    Google Scholar 

  13. Clarke Jr., E.M., Grumberg, O., Peled, D.A.: Model Checking. MIT Press, Cambridge (1999)

    MATH  Google Scholar 

  14. Biere, A., Cimatti, A., Clarke, E.M., Zhu, Y.: Symbolic Model Checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  15. Miller, D.M., Thornton, M.A.: QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. In: Int’l Symp. on Multiple-Valued Logic, p. 30. IEEE Computer Society (May 2006)

    Google Scholar 

  16. Biere, A., Cimatti, A., Clarke, E.M., Strichman, O., Zhu, Y.: Bounded model checking. Advances in Computers 58, 117–148 (2003)

    Article  Google Scholar 

  17. Wille, R., Große, D., Miller, D.M., Drechsler, R.: Equivalence Checking of Reversible Circuits. In: Int’l Symp. on Multiple-Valued Logic, pp. 324–330. IEEE Computer Society (May 2009)

    Google Scholar 

  18. Gay, S.J., Nagarajan, R., Papanikolaou, N.: QMC: A Model Checker for Quantum Systems. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 543–547. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  19. Aaronson, S., Gottesman, D.: Improved simulation of stabilizer circuits. Phys. Rev. A 70, 052328 (2004)

    Article  Google Scholar 

  20. Vidal, G.: Efficient Classical Simulation of Slightly Entangled Quantum Computations. Phys. Rev. Letters 91, 147902 (2003)

    Article  Google Scholar 

  21. Viamontes, G.F., Markov, I.L., Hayes, J.P.: Quantum Circuit Simulation. Springer, Heidelberg (2009)

    Book  MATH  Google Scholar 

  22. Deutsch, D.: Quantum Theory, the Church-Turing Principle and the Universal Quantum Computer. Royal Society London A 400(1818) (July 1985)

    Google Scholar 

  23. Miller, D.M., Wille, R., Dueck, G.: Synthesizing Reversible Circuits for Irreversible Functions. In: EUROMICRO Symp. on Digital System Design, pp. 749–756 (2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Seiter, J., Soeken, M., Wille, R., Drechsler, R. (2013). Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. In: Glück, R., Yokoyama, T. (eds) Reversible Computation. RC 2012. Lecture Notes in Computer Science, vol 7581. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36315-3_15

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-36315-3_15

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36314-6

  • Online ISBN: 978-3-642-36315-3

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics