Abstract
Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for near-threshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ickes, N., et al.: A 28nm 0.6V Low-Power DSP for Mobile Applications. IEEE JSSC 47(1), 35–46 (2012)
Jain, S., et al.: A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS. In: Proc. ISSCC, pp. 66–68 (February 2012)
Abouzeid, F., et al.: 40nm CMOS 0.35V-Optimized Standard Cell Library for Ultra-Low Power Applications. ACM TODAES 16(3), Article 35 (June 2011)
Kung, D.S., et al.: Optimal P/N Width Ratio Selection for Standard Cell Libraries. In: Proc. ICCAD, pp. 178–184 (November 1999)
Hanson, S., Sylvester, D., Blaauw, D.: A New Technique for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits. In: Proc. of ISLPED, pp. 338–341 (October 2006)
Bol, D., Ambroise, R., Flandre, D., Legat, J.-D.: Impact of Technology Scaling on Digital Subthreshold Circuits. In: Proc. of ISVLSI, pp. 179–184 (April 2008)
Emadi, M., Jafargholi, A., Moghadam, H.S., Nayebi, M.M.: Optimum Supply and Threshold Voltages and Transistor Sizing Effect on Low Power SOI Circuit Design. In: Proc. of APCCAS, pp. 1394–1398 (December 2006)
Hansen, M.C., Yalcin, H., Hayes, J.P.: Unveiling the ISCAS-85 benchmarks: A Case Study in Reverse Engineering. IEEE Design & Test of Computers 16(3), 72–80 (1999)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kondo, M., Nishizawa, S., Ishihara, T., Onodera, H. (2013). A Standard Cell Optimization Method for Near-Threshold Voltage Operations. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_4
Download citation
DOI: https://doi.org/10.1007/978-3-642-36157-9_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36156-2
Online ISBN: 978-3-642-36157-9
eBook Packages: Computer ScienceComputer Science (R0)