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Advances in Parallel Transistor-Level Circuit Simulation

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Scientific Computing in Electrical Engineering SCEE 2010

Part of the book series: Mathematics in Industry ((TECMI,volume 16))

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Abstract

Parallel transistor-level circuit simulation has the potential to significantly impact the need for reliably determining parasitic effects for modern feature sizes. Incorporating parallelism into a simulator at both coarse and fine-grained levels, through the use of message-passing and threading paradigms, is supported by the advent of inexpensive clusters, as well as multi-core technology. However, its effectiveness is reliant upon the development of efficient parallel algorithms for traditional “true SPICE” circuit simulation. In this paper, we will discuss recent advances in fully parallel transistor-level full-chip circuit simulation, concluding with scaling results from a newer strategy for the parallel preconditioned iterative solution of circuit matrices.

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References

  1. Cadence UltraSim. http://www.cadence.com/products/custom_ic/ultrasim/

  2. Nascentric OmegaSim. http://www.nascentric.com/omegasim_gx.html

  3. Synopsys HSIM. http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimu-

  4. Synopsys HSPICE. http://www.synopsys.com/Tools/Verification/AMSVerification/Circuit-

  5. Synopsys NanoSim. http://www.synopsys.com/Tools/Verification/AMSVerification/Circuit-

  6. Xyce Parallel Circuit Simulator. http://xyce.sandia.gov

  7. Basermann, A., Jaekel, U., Nordhausen, M.: Parallel iterative solvers for sparse linear systems in circuit simulation. Fut. Gen. Comput. Sys. 21(8), 1275–1284 (2005)

    Article  Google Scholar 

  8. Bomhof, C., vanderVorst, H.: A parallel linear system solver for circuit simulation problems. Num. Lin. Alg. Appl. 7(7–8), 649–665 (2000)

    Google Scholar 

  9. Davis, T.A.: Direct Methods for Sparse Linear System. SIAM, Philadelphia (2006)

    Book  Google Scholar 

  10. Dong, W., Li, P., Ye, X.: Wavepipe: Parallel transient simulation of analog and digital circuits on multi-core shared-memory machines. In: IEEE/ACM Design Automation Conference, pp. 238–243 (2008)

    Google Scholar 

  11. Fröhlich, N., Riess, B., Wever, U., Zheng, Q.: A new approach for parallel simulation of VLSI-circuits on a transistor level. IEEE Trans. Circ. Sys. Part I 45(6), 601–613 (1998)

    Article  Google Scholar 

  12. Gropp, W., Lusk, E., Doss, N., Skjellum, A.: A high-performance, portable implementation of the MPI message passing interface standard. Parallel Computing 22(6), 789–828 (1996)

    Article  MATH  Google Scholar 

  13. Gulati, K., Croix, J.F., Khatr, S.P., Shastry, R.: Fast circuit simulation on graphics processing units. In: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 403–408. IEEE Press (2009)

    Google Scholar 

  14. Heidi K. Thornquist et al.: A parallel preconditioning strategy for efficient transistor–level circuit simulation. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 410–417 (2009)

    Google Scholar 

  15. Kundert, K.: Sparse matrix techniques. In: A. Ruehli (ed.) Circuit Analysis, Simulation and Design. North-Holland, New York (1987)

    Google Scholar 

  16. Li, X.S., Demmel, J.W.: SuperLU_DIST: A scalable distributed-memory sparse direct solver for unsymmetric linear systems. ACM Trans. Math. Softw. 29(2), 110–140 (2003)

    Article  MATH  MathSciNet  Google Scholar 

  17. Nagel, L.W.: Spice 2, a computer program to simulate semiconductor circuits. Tech. Rep. Memorandum ERL-M250 (1975)

    Google Scholar 

  18. Nassif, J.N.K.S.R., Najm, F.N.: A multigrid-like technique for power grid analysis. IEEE Trans. Computer-Aided Des. 21, 1148–1160 (2002)

    Google Scholar 

  19. Peng, H., Cheng, C.K.: Parallel transistor level circuit simulation using domain decomposition methods. In: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 397–402. IEEE Press (2009)

    Google Scholar 

  20. Saad, Y., Schultz, M.H.: GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems. SIAM J. Sci. Comput. 7(3), 856–869 (1986)

    Article  MATH  MathSciNet  Google Scholar 

  21. Schenk, O., Gärtner, K.: Solving unsymmetric sparse systems of linear equations with PARDISO. Fut. Gen. Comput. Sys. 20(3), 475–487 (2005)

    Article  Google Scholar 

  22. Stanley, K., Davis, T.: KLU: a ’Clark Kent’ sparse LU factorization algorithm for circuit matrices. In: SIAM Conference on Parallel Processing for Scientfic Computing (PP04) (2004)

    Google Scholar 

  23. Sun, K., Zhou, Q., Mohanram, K., Sorensen, D.C.: Parallel domain decomposition for simulation of large-scale power grids. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 54–59 (2007)

    Google Scholar 

  24. Ye, X., Dong, W., Li, P., Nassif, S.: MAPS: Multi-algorithm parallel circuit simulation. In: IEEE/ACM International Conference on Computer-Aided Design, pp. 73–38 (2008)

    Google Scholar 

  25. Zhuo, C., Hu, J., Zhao, M., Chen, K.: Power grid analysis and optimization using algebraic multigrid. IEEE Trans. Computer-Aided Des. 27, 738–751 (2008)

    Article  Google Scholar 

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Acknowledgements

The authors would like to thank David Day, Erik Boman, Mike Heroux, Ray Tuminaro, and Scott Hutchinson for many helpful discussions. We would also like to thank the Xyce development team, including Tom Russo and Rich Schiek.

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Authors and Affiliations

  1. Electrical Systems Modeling Department, Sandia National Laboratories, 5800, Albuquerque, NM, 87185-0316, USA

    Heidi K. Thornquist & Eric R. Keiter

Authors
  1. Heidi K. Thornquist
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  2. Eric R. Keiter
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Corresponding author

Correspondence to Heidi K. Thornquist .

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Editors and Affiliations

  1. ONERA, avenue Édouard Belin 2, Toulouse, 31055, France

    Bastiaan Michielsen

  2. LAPLACE-ENSEEIHT, rue Charles Camichel 2, Toulouse, 31071, France

    Jean-René Poirier

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Thornquist, H.K., Keiter, E.R. (2012). Advances in Parallel Transistor-Level Circuit Simulation. In: Michielsen, B., Poirier, JR. (eds) Scientific Computing in Electrical Engineering SCEE 2010. Mathematics in Industry(), vol 16. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22453-9_27

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