Abstract
The transconductance is one of the main device parameters used to analyze the electrical characteristics of the MOSFET. From the transconductance versus gate voltage characteristic it is possible to extract many electrical and technological parameters like threshold voltage, carrier mobility, electric field mobility degradation and others. However, partially and fully depleted SOI (planar and multi-gate) devices present second order effects that have to be well understood in order to avoid any mistake of the parameter extraction. This chapter is devoted to show the main second order effects that modify the transconductance behavior from micro to nano era of SOI devices like: partially-depleted, fully depleted, planar and multi-gate, standard and strained, DTMOS and GC SOI MOSFETs. The impact of the gate stack composition such as cap layer and metal gate thickness is also outlined. For example multiple gm peaks are sometimes observed and can be related with different origins like gate induced floating body effects, multiple threshold voltages, quantum effects and others.
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Martino, J.A., Agopian, P.G.D., Simoen, E., Claeys, C. (2011). SOI MOSFET Transconductance Behavior from Micro to Nano Era. In: Nazarov, A., Colinge, JP., Balestra, F., Raskin, JP., Gamiz, F., Lysenko, V. (eds) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15868-1_15
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