Abstract
In recent years, transaction level modeling (TLM) has enabled designers to simulate complex embedded systems and SoCs, orders of magnitude faster than simulation at the RTL. The increasing complexity of the systems on one hand, and availability of low cost parallel processing resources on the other hand have motivated the development of parallel simulation environments for TLMs. The existing simulation environments used for parallel simulation of TLMs are intended for general discrete event models and do not take advantage of the specific properties of TLMs. The fine-grain synchronization and communication between simulators in these environments can become a major impediment to the efficiency of the simulation environment. In this work, we exploit the properties of temporally decoupled TLMs to increase the efficiency of parallel simulation. Our approach does not require a special simulation kernel. We have implemented a parallel TLM simulation framework based on the publicly available OSCI SystemC simulator. The framework is based on the communication interfaces proposed in the recent OSCI TLM 2 standard. Our experimental results show the reduced synchronization overhead and improved simulation performance.
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Salimi Khaligh, R., Radetzki, M. (2009). Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. In: Rettberg, A., Zanella, M.C., Amann, M., Keckeisen, M., Rammig, F.J. (eds) Analysis, Architectures and Modelling of Embedded Systems. IESS 2009. IFIP Advances in Information and Communication Technology, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04284-3_14
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DOI: https://doi.org/10.1007/978-3-642-04284-3_14
Publisher Name: Springer, Berlin, Heidelberg
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