Abstract
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware units (e.g., level one (L1) and level two (L2) caches, functional units, registers) are selected based on a set of specifications for a particular application. Currently, chip architects are using software tools to manually explore different configurations, so that tradeoffs for power consumption, performance, and chip size may be understood. The primary contribution of this paper is the development of a novel power-performance design tool based around a core GA search and optimization technique. The tool targets the implementation of portable embedded systems.
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Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. of the 27th International Symposium on Computer Architecture, Vancouver, BC, June 2000, pp. 83–94 (2000)
Roth, A.: online at http://www.cis.upenn.edu/~amir/cis501-01 , CIS 501: Introduction to Computer Architecture, University of Pennsylvania (2001)
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Northern, J., Shanblatt, M. (2004). A Multi-objective Approach to Configuring Embedded System Architectures. In: Deb, K. (eds) Genetic and Evolutionary Computation – GECCO 2004. GECCO 2004. Lecture Notes in Computer Science, vol 3103. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24855-2_149
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DOI: https://doi.org/10.1007/978-3-540-24855-2_149
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22343-6
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