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Formal Verification of SystemC-based Cyber Components

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Industrial Internet of Things

Part of the book series: Springer Series in Wireless Technology ((SSWT))

Abstract

Cyber-Physical Systems (CPS) integrate physical and cyber components, where the latter are responsible for the computation part. Due to their steadily increasing complexity, these cyber components have to be modeled at high level of abstraction when creating a new CPS. Therefore, the Electronic System Level (ESL) emerged and a widely accepted ESL design language is SystemC. The main driver for abstraction in SystemC is Transaction Level Modeling (TLM) which allows describing complex communication without all the details. Since the SystemC TLM models are used for early software development and as reference for hardware implementation their correct functional behavior is crucial. Admittedly, the best possible verification quality can be achieved with formal approaches. However, formal verification of TLM models is a hard task. Existing methods basically consider local properties or have extremely high run-time. In contrast, the proposed approach can efficiently verify true TLM properties, for instance the effect of a transaction can be formally checked which has not been possible before. Our approach transforms the SystemC model to C, embeds the TLM property in form of assertions into the C model and finally uses a novel induction to check the validity of the property. The induction method is essentially a lifting of inductive bounded model checking to C. In experiments we show the efficiency of the approach.

This chapter is an extended version of a conference paper appeared at MEMOCODE 2010 [1].

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Notes

  1. 1.

    www.systemc-verification.org/sciver.

  2. 2.

    In the considered TLM models there are no clocks. We only use the clock expression syntax to define sampling points.

  3. 3.

    C model checkers typically support an assumption concept, i.e. assertions are checked for all execution paths of the program that satisfy the assumptions.

  4. 4.

    Our benchmarks can be found on the SCIVER Website: www.systemc-verification.org/sciver.

  5. 5.

    Their experiments were done on a 2 GHz AMD Opteron system with 4 GB RAM running Linux.

References

  1. Große D, Le HM, Drechsler R (2010) Proving transaction and system-level properties of untimed SystemC TLM designs. In: ACM and IEEE international conference on formal methods and models for codesign, pp 113–122

    Google Scholar 

  2. Bailey B, Martin G, Piziali A (2007) ESL design and verification: a prescription for electronic system level methodology. Morgan Kaufmann, Amsterdam

    Google Scholar 

  3. IEEE Standard for Standard SystemC Language Reference Manual (2012) IEEE Std. 1666

    Google Scholar 

  4. Pasricha S (2002) Transaction level modeling of SoC with SystemC 2.0. In: SNUG

    Google Scholar 

  5. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, pp 19–24

    Google Scholar 

  6. Ghenassia F (2006) Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems. Springer, US

    Google Scholar 

  7. Vardi MY (2007) Formal techniques for SystemC verification. In: Design Automation Conference, pp 188–192

    Google Scholar 

  8. Dahan A, Geist D, Gluhovsky L, Pidan D, Shapir G, Wolfsthal Y, Benalycherif L, Kamdem R, Lahbib Y (2005) Combining system level modeling with assertion based verification. In: ISQED, pp 310–315

    Google Scholar 

  9. Ecker W, Esen V, Hull M, Steininger T, Velten M (2006) Requirements and concepts for transaction level assertions. In: International conference on computer design, pp 286–293

    Google Scholar 

  10. Bombieri N, Fummi F, Pravadelli G (2007) Incremental ABV for functional validation of TL-to-RTL design refinement. In: Design, automation and test in Europe, pp 882–887

    Google Scholar 

  11. Ferro L, Pierre L (2009) ISIS: runtime verification of TLM platforms. In: Forum on specification and design languages, pp 1–6

    Google Scholar 

  12. Tabakov D, Vardi MY (2010) Monitoring temporal SystemC properties. In: ACM and IEEE international conference on formal methods and models for codesign, pp 123–132

    Google Scholar 

  13. Ferro L, Pierre L, Amor ZBH, Lachaize J, Lefftz V (2011) Runtime verification of typical requirements for a space critical SoC platform. In: FMICS, pp 21–36

    Google Scholar 

  14. Cimatti A, Narasamdya I, Roveri M (2011) Boosting lazy abstraction for SystemC with partial order reduction. In: Tools and algorithms for the construction and analysis of systems, pp 341–356

    Google Scholar 

  15. Habibi A, Tahar S (2005) Design for verification of SystemC transaction level models. In: Design, automation and test in Europe, pp 560–565

    Google Scholar 

  16. Moy M, Maraninchi F, Maillet-Contoz L (2006) LusSy: an open tool for the analysis of systems-on-a-chip at the transaction level. In: Design automation for embedded systems, pp 73–104

    Google Scholar 

  17. Karlsson D, Eles P, Peng Z (2006) Formal verification of SystemC designs using a petri-net based representation. In: Design, automation and test in Europe, pp 1228–1233

    Google Scholar 

  18. Niemann B, Haubelt C (2006) Formalizing TLM with communicating state machines. In: Forum on specification and design languages, pp 285–293

    Google Scholar 

  19. Traulsen C, Cornet J, Moy M, Maraninchi F (2007) A SystemC/TLM semantics in Promela and its possible applications. In: SPIN, pp 204–222

    Google Scholar 

  20. Helmstetter C, Ponsini O (2008) A comparison of two SystemC/TLM semantics for formal verification. In: ACM and IEEE international conference on formal methods and models for codesign, pp 59–68

    Google Scholar 

  21. Herber P, Fellmuth J, Glesner S (2008) Model checking SystemC designs using timed automata. In: IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, pp 131–136

    Google Scholar 

  22. Kundu S, Ganai M, Gupta R (2008) Partial order reduction for scalable testing of SystemC TLM designs. In: Design automation conference, pp 936–941

    Google Scholar 

  23. Blanc N, Kroening D (2008) Race analysis for SystemC using model checking. In: International conference on CAD, pp 356–363

    Google Scholar 

  24. Cimatti A, Micheli A, Narasamdya I, Roveri M (2010) Verifying SystemC: a software model checking approach. In: International conference on formal methods in CAD, pp 51–60

    Google Scholar 

  25. Tabakov D, Vardi M, Kamhi G, Singerman E (2008) A temporal language for SystemC. In: International conference on formal methods in CAD, pp 1–9

    Google Scholar 

  26. Accellera Property Specification Language Reference Manual (2005) version 1.1. http://www.pslsugar.org

  27. Chou C-N, Ho Y-S, Hsieh C, Huang C-Y (2012) Symbolic model checking on SystemC designs. In: Design automation conference, pp 327–333

    Google Scholar 

  28. Le HM, Große D, Herdt V, Drechsler R (2013) Verifying SystemC using an intermediate verification language and symbolic simulation. In: Design automation conference, pp 116:1–116:6

    Google Scholar 

  29. Herdt V, Le HM, Drechsler R (2015) Verifying SystemC using stateful symbolic simulation. In: Design automation conference, pp 49:1–49:6

    Google Scholar 

  30. Biere A, Cimatti A, Clarke EM, Zhu Y (1999) Symbolic model checking without BDDs. In: Tools and algorithms for the construction and analysis of systems, pp 193–207

    Google Scholar 

  31. Sheeran M, Singh S, Stålmarck G (2000) Checking safety properties using induction and a SAT-solver. In: International conference on formal methods in CAD, pp 108–125

    Google Scholar 

  32. Bjesse P, Claessen K (2000) SAT-based verification without state space traversal. In: International conference on formal methods in CAD, pp 372–389

    Google Scholar 

  33. Clarke EM, Kroening D, Lerda F (2004) A tool for checking ANSI-C programs. In: Tools and algorithms for the construction and analysis of systems, pp 168–176

    Google Scholar 

  34. Brummayer R, Biere A (2009) Boolector: an efficient SMT solver for bit-vectors and arrays. In: Tools and algorithms for the construction and analysis of systems, pp 174–177

    Google Scholar 

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Correspondence to Daniel Große .

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Große, D., Le, H.M., Drechsler, R. (2017). Formal Verification of SystemC-based Cyber Components. In: Jeschke, S., Brecher, C., Song, H., Rawat, D. (eds) Industrial Internet of Things. Springer Series in Wireless Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-42559-7_6

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  • DOI: https://doi.org/10.1007/978-3-319-42559-7_6

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