Abstract
The developed Parasitic Extractor targets layout-aware integrated circuit sizing methodologies due to its ability to run accurately not only over a complete layout, but also over an incomplete layout, which has only the non-detailed routing (i.e., the global routing). This feature greatly reduces the required computational time in layout-aware loops, due to complexity required to automatically generate the detailed routing, which is avoided. However, designers’ must have the accuracy of industry “standard” extraction tools, hence, it is mandatory to have high accuracy in the values of the parasitic structures identified, even in a simplified extraction procedure. On the other side, it should be practical to use, hence a minimum set of inputs is considered. The empirical-based Parasitic Extractor inputs only the floorplan solution generated by an automatic Placer, the global routing solution, and the intercap models provided by the foundry that contain the standard interconnect capacitance values. This Chapter explains all the methods used in the empirical-based Parasitic Extractor to accurately compute the parasitic structures, from the processing of the intercap models tables to the extraction of all resistive and capacitive structures.
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Martins, R., Lourenço, N., Horta, N. (2017). Empirical-Based Parasitic Extractor. In: Analog Integrated Circuit Design Automation. Springer, Cham. https://doi.org/10.1007/978-3-319-34060-9_7
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DOI: https://doi.org/10.1007/978-3-319-34060-9_7
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