Abstract
Fine-time resolution measurements are attracting increasing attention in the high-energy-physics (HEP) community, where a large number of measurement channels must often be realized with a single ASIC. In this contribution, a multi-channel time-to-digital converter (TDC) architecture with a delay-locked-loop (DLL) in its first stage and a resistive interpolation scheme in its second stage is presented. The size of the TDC’s least-significant-bit (LSB) is controlled by a reference clock and so can be continuously adjusted from 5 to 20 ps. A global calibration scheme that avoids the need to calibrate each channel separately is also used. Critical design aspects like device mismatch, supply noise sensitivity and process-voltage and temperature (PVT) variation are discussed. When realized in a 130 nm technology, the prototype ASIC achieved a single-shot resolution of better than 2.5 ps-rms. The measured integral-non-linearity (INL) and differential-non-linearity (DNL) were found to be ±1.4 LSB and ±0.9 LSB respectively.
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Perktold, L., Christiansen, J. (2015). Fine-Time Resolution Measurements for High Energy Physics Experiments. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_14
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DOI: https://doi.org/10.1007/978-3-319-07938-7_14
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