A Global Routing Optimization Scheme Based on ABC Algorithm

Abstract

Rapid technological advancements are leading to a continuous reduction of integrated chip sizes. An additional steady increase in the chip density is resulting in device performance improvements as well as severely complicating the fabrication process. The interconnection of all the components on a chip, known as routing, is done in two phases: global routing and detail routing. These phases impact chip performance significantly and hence researched extensively today. This paper deals with the global routing phase which is essentially a case of finding a Minimal Rectilinear Steiner Tree (MRST) by joining all the terminal nodes, known to be an NP-hard problem. There are several algorithms which return near optimal results. Recently algorithms based on Evolutionary Algorithms (such as Genetic Algorithm) and based on Swarm Intelligence (such as PSO, ACO, ABC, etc.) are being increasingly used in the domain of global routing optimization of VLSI Design. Swarm based algorithms are an emerging area in the field of optimization and this paper presents a swarm intelligence algorithm, Artificial Bee Colony(ABC) for solving the routing optimization problem. The proposed algorithm shows noteworthy improvements in reduction of the total interconnect length. The performance of this algorithm has been compared with FLUTE (Fast Look Up Table Estimation) that uses Look Up Table to handle nets with degree up to 9 and net breaking technique for nets with degree up to 100. It is used for VLSI applications in which most of the nets have a degree 30 or less than that.