Abstract
In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
X. Huang, et al., IEDM Tech. Dig., 1999, p. 67–70.
J. Kedzierski et al., IEDM Tech. Dig., 2001, p. 437–440.
R. Chau, et al., Extended Abstracts of International Conference on Solid State Devices & Materials (SSDM), Nagoya, Japan, 2002, p.68–69.
E. M. Buturla, et al., IBM J. Res. Develop., vol. 25, p. 218, 1981.
D. Mountain, IEEE Trans. Electron Devices, vol. 36, p. 2499–504, 1989.
S. E. Laux, IEEE Trans. Electron Devices, vol. 4, pp. 472–481, 1985.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer-Verlag Wien
About this paper
Cite this paper
Wang, X., Bryant, A., Dokumaci, O., Oldiges, P., Haensch, W. (2007). Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond. In: Grasser, T., Selberherr, S. (eds) Simulation of Semiconductor Processes and Devices 2007. Springer, Vienna. https://doi.org/10.1007/978-3-211-72861-1_30
Download citation
DOI: https://doi.org/10.1007/978-3-211-72861-1_30
Publisher Name: Springer, Vienna
Print ISBN: 978-3-211-72860-4
Online ISBN: 978-3-211-72861-1
eBook Packages: EngineeringEngineering (R0)