Abstract
So far in the book we have always used a synchronous clock edge as the sampling edge for the assertion. That is for good reason. The example presented here uses an asynchronous edge (perfectly legal) as the sampling edge. The problem statement goes something like “whenever (i.e. asynchronously) L2TxData==L2ErrorData that L2Abort is asserted”. Now that looks very logical to implement without the need for a clock. So, we write a property as shown in the Fig. 15.1. We simply say that @ (L2TxData) (i.e. whenever L2TxData changes) that we compare L2TxData == L2ErrorData and if that matches we imply that L2Abort == 1.
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© 2014 Springer Science+Business Media New York
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Mehta, A.B. (2014). Asynchronous Assertions !!! . In: SystemVerilog Assertions and Functional Coverage. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7324-4_15
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DOI: https://doi.org/10.1007/978-1-4614-7324-4_15
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