Abstract
This paper presents the performance of the static timing analyzer TAS for deep sub-micronic CMOS technologies. The methodology used by TAS is given with special emphasis on its Short Channel MOS model. Results are given to show the accuracy of the static timing analyzer TAS for various CMOS circuits (including pass transistor and precharge logic) as well as for various CMOS processes ranging from 1.2μ to 0.35μ. The Short Channel MOS model of TAS appears to be relevant to the analysis of deep submicronic processes.
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References
Advanced Micro Device (1977) Data sheet of the amd2901.
Anacad - Mentor Graphics Inc. (1996) Eldo User’s Manual.
Auvergne, D., Azemard, A., Deschacht, D. and Robert, M. (1990) Input waveform slope effects in CMOS delays. IEEE J. of Solid-State Circuits, 25, 1588–3.
Bazargan-Sabet, P., Burgun, L., Greiner, A. and Pétrot, F. (1994) Methodology and development of a complete CAD system for digital VLSI design, in Proc. VIII Simposio Brasileiro de Concepcao de Circuitos Integrados, Gramado, 11–5.
Benkoski, J., Vanden Meersch, E., Claesen, L.J.M. and De Man, H. (1990) Timing verification using statically sensitizable paths. IEEE Trans. on Computer-Aided Design, 9, 1073–12.
Chandramouli, V. and Sakallah, K.A. (1996) Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time, in Proc. 33rd Design Automation Conference, Las Vegas.
Cheng, S.W., Chen, H.C., Du, D.H.C. and Lim, A. (1992) The role of long and short paths in circuit performance optimization, in Proc. ACM/IEEE Design Automation Conference, Anaheim, 543–6.
Dagenais, M.R., Gaiotti, S. and Rumin, N.C. (1992) Transistor-level estimation of worst case delays in MOS VLSI circuits. IEEE Trans. on Computer-Aided Design, 11, 384–12.
Dioury, K. and Rosset-Louërat, M.-M. (1997) Fitting the technoly file for the static timing analyser TAS. LIP6, Université Pierre et Marie Curie, Paris.
Greiner, A., Laurentin, M. and Marbot, R. (1992) DESB, a functional abstractor for CMOS VLSI circuits, in Proc. European Design Automation Conference, Hamburg, 22–6.
Greiner, A. and Pétrot, F. (1994) A public domain high performances portable ROM generator, in Proc. 20th Euromicro, Liverpool, 414–6.
Hajjar, A., Marbot, R., Greiner, A. and Kiani. P. (1991) TAS: An accurate timing analyser for CMOS VLSI, in Proc. 2nd European Conference on Design Automation, Amsterdam, 261–6.
Hajjar, A. (1992) Modélisation des temps de propagation et analyse temporelle statique des circuits intégrés CMOS. PHD Thesis, Paris, Université Pierre et Marie Curie.
Lester, A. (1994) YAGLE: Yet Another Gate Level Extractor. LIP6, Université Pierre et Marie Curie, Paris.
Lucas, L., Greiner, A. and Thill, M. (1993) High speed adder generator, in Proc. 5th International Conference on Microelectronic, Dhahran, 136–4.
Nagel, L.W. (1975) SPICE2: A computer program to simulate semiconductor circuits. University of California, ERL Memo ERL-M520, Berkekey.
Ousterhout, J.K. (1985) A switch-level timing verifier for digital MOS VLSI. IEEE Trans. on Computer-Aided Design, CAD-4, 336–14.
Perremans, S., Claesen, L. and De Man, H. (1989) Static timing analysis of dynamically sensitizable paths, in Proc. 26th ACM/IEEE Design Automation conference, 568–6.
Royannez, P., Greiner, A. and Amara, A. (1994) Booth multi-pipelined multiplier generator, in Proc. the IX Congressoda Sociedade Brasileira de Microelectronica (SBMICRO), Rio de Janeiro, 686–4.
Sakurai, T. and Newton, A.R. (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. of Solid-State Circuits, 25, 584–11.
Sakurai, T. and Newton, A.R. (1991) Delay analysis of series-connected MOSFET circuits IEEE J. of solid-state circuits, 26, 122–10.
Sangiovanni-Vincentelli, A.L., Mc Geer, P.C. and Saldanha, A. (1996) Verification of electronic systems, in Proc. 33rd Design Automation Conference, Las Vegas.
Schulz, S.E. (1995) Timing analysis tools and trends. Integrated System Design Magazine, nov.
Turgis, S., Daga, J.M., Portal, J.M. and Auvergne, D. (1997) Internal power modelling and minimization in CMOS inverters, in Proc. The European Design Test Conference, Paris, 603–6.
Wunder, B., Lehmann, G. and Müller-Glaser, K.D. (1996) VAMP: a VHDL based concept for accurate modeling and post layout timing simulation of electronic systems, in Proc. 33rd Design Automation Conference, Las Vegas.
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© 1997 Springer Science+Business Media Dordrecht
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Dioury, K., Greiner, A., Rosset-Louërat, MM. (1997). Accurate static timing analysis for deep submicronic CMOS circuits. In: Reis, R., Claesen, L. (eds) VLSI: Integrated Systems on Silicon. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35311-1_36
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DOI: https://doi.org/10.1007/978-0-387-35311-1_36
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