Abstract
This paper presents an innovative DVS technique to reduce the energy dissipation. Our objective is to minimize the transitions between power modes by maximizing the idle periods of functional units with instruction scheduling. Our work first analyzes the control flow graph of the application, which contains many regions. Second, we collect the power information and build its power model for each region. Then two regions with the same functional units will be merged if no dependencies exist between them. The process is repeated until no further mergings can be performed. Next, the idle functional units will be turned off and each region will be assigned a power mode based on the power model. Finally, the application is rescheduled to merge the regions to reduce the transitions between power modes. The experimental results show that our work can save the energy by 26%.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
AbouGhazaleh, N., Moss’e, D., Childers, B., Melhem, R.: Toward the placement of power management points in real time applications. In: Proceedings of the Workshop on Compilers and Operating Systems for Low Power (September 2001)
Alpha, Alpha 21264 Processor Technical Reference Manual, http://www.alpha.com
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural Level Power Analysis and Optimizations. In: International Symposium on Computer Architecture (ISCA), Vanconver, British Columbia (2000)
Burd, T., Brodersen, R.: Design issues for dynamic voltage scaling. In: Proceedings of 2000 International Symposium on Low Power Electronics and Design (July 2000)
Hsu, C.H., Kremer, U.: Compiler-directed dynamic voltage scaling based on program regions. Technical Report DCS-TR-461, Department of Computer Science, Rutgers University (November 2001)
Hsu, C.H., Kremer, U.: Single region vs. multiple regions: A comparison of different compiler-directed dynamic voltage scheduling approaches. In: Workshop on Power-Aware Computer Systems (2002)
Hsu, C.H., Kremer, U.: The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction. In: Proceedings of the ACM SIGPLAN Conference on Programming Languages Design and Implementation (June 2003)
Krishna, C.M., Lee, Y.-H.: Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems. In: Proceedings of the 6th Real Time Technology and Applications Symposium (RTAS 2000) (May 2000)
MachSuif: A Framework built on top of SUIF for building back-ends, http://www.eecs.harvard.edu/~hube
Manzak, A., Chakrabarti, C.: Variable voltage task scheduling for minimizing energy or minimizing power. In: Proceeding of the International Conference on Acoustics, Speech and Signal Processing (June 2000)
Roy, K.: Leakage Power Reduction in Low-Voltage CMOS Design. In: IEEE International Conference on Circuits and Systems, pp. 167–173 (1998)
Sannella, M.J.: Constraint Satisfaction and Debugging for Interactive User Interfaces. Ph.D. Thesis, University of Washington, Seattle, WA (1994)
Shin, D., Kim, J., Lee, S.: Intra-task voltage scheduling for low-energy hard real-time applications. IEEE Design and Test of Computers 18(2) (March/April 2001)
SUIF: Stanford University Intermediate Format, http://suif.stanford.edu
Transmeta, Crusoe TM5800 Processor Technical Reference Manual, http://transmeta.com/
You, Y.-P., Lee, C., Lee, J.K.: Compilers for Leakage Power Reduction. ACM Transactions on Design Automation of Electronic Systems (accepted)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lin, TY., Chang, RG. (2006). Power-Aware Instruction Scheduling. In: Sha, E., Han, SK., Xu, CZ., Kim, MH., Yang, L.T., Xiao, B. (eds) Embedded and Ubiquitous Computing. EUC 2006. Lecture Notes in Computer Science, vol 4096. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802167_6
Download citation
DOI: https://doi.org/10.1007/11802167_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36679-9
Online ISBN: 978-3-540-36681-2
eBook Packages: Computer ScienceComputer Science (R0)