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A High-Speed Pseudorandom Test Pattern Generator

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Abstract

Real-time built-in self-testing (BIST) of digital devices that incorporate functional modules of various speed is considered. A method of designing a pattern generator is suggested. This generator is capable of forming pseudorandom test patterns both with the normal speed (one test vector per clock cycle) and with a speed several times higher (several test vectors per clock cycle). With these generators, at-speed testing of multichip module components can be performed to detect both stuck-at and ac faults.

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REFERENCES

  1. Rajski, J. and Kuyl, M., Design-for-Test for System-on-Chip Design, Proc. Design&Diagnostics of Electronic Circuit&Systems, 1998, pp. 203-209.

  2. Doane, D.A. and Franzon, P.D., Multi-Chip Module Technologies and Alternatives-The Basics, Van Nostrand Reinhold, 1993.

  3. Foote, T. et al., Testing the 400-MHz IBM Generation-4 CMOS Chip, Proc. Int. Test Conf., 1997, pp. 101-105.

  4. Pyron, C., Prado, J., and Golab, J., Next-Generation PowerPC Microprocessor Test Strategy Improvements, Proc. Int. Test Conf., 1997, pp. 414-423.

  5. Riesco, J. et al., On the Way to the 2.5 Gbits/s ATM Network ATM Multiplexer Demultiplexer ASIC, Proc. European Design and Test Conf., 1997, pp. 218-222.

  6. Potts, D. and Griesmer, R., A Unique Methodology for At-Speed Testing of cDSP(TM) and ASIC Devices, Proc. Int. Test Conf., 1996, pp. 701-707.

  7. Keezer, D.C. and Wenzel, R.J., Low Cost ATE Pin Electronics for a Multi-Gigabit-Per-Second At-Speed Test, Proc. Int. Test Conf., 1997, pp. 94-100.

  8. Golomb, S.W., Shift Register Sequences, San-Francisko: Holden Day, 1967.

    Google Scholar 

  9. Chamzas, C.C., Parasitic Spectral Lines in High Speed Generation of Binary Maximum Length Sequences, IEEE Trans. Commun., 1978, vol. 26, no. 6, pp. 922-925.

    Google Scholar 

  10. Lempel, A. and Eastman, W.L., High Speed Generation of Maximal Length Sequences, IEEE Trans. Comput., 1971, vol. 20, no. 24, pp. 227-229.

    Google Scholar 

  11. Yarmolik, V.N. and Murashko, I.A., Designing a Test Pattern Generator Based on the M-Sequence Decimation Property, Avtom. Vychisl. Tekh., 1997, no. 1, pp. 44-56.

    Google Scholar 

  12. Bardell, P.H., Discrete Logarithms: A Parallel Pseudorandom Pattern Generator Analysis Method, J. Elect. Testing: Theory and Appl., 1992, vol. 3, pp. 17-31.

    Google Scholar 

  13. Rajsky, J. and Tyszer, J., Design of Phase Shifter for BIST Applications, 16th IEEE VLSI Test Symp., 1998, pp. 218-224.

  14. Murashko, I.A., Shmidman, A.M., and Yarmolik, V.N., A New Approach to Designing Scan Chains for VLSI BIST, Avtom. Telemekh., 1998, no. 7, pp. 157-167.

    Google Scholar 

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Authors and Affiliations

  1. Gomel Polytechnical Institute, Gomel, Belarus

    I. A. Murashko & V. N. Yarmolik

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  1. I. A. Murashko
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  2. V. N. Yarmolik
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Murashko, I.A., Yarmolik, V.N. A High-Speed Pseudorandom Test Pattern Generator. Russian Microelectronics 30, 59–66 (2001). https://doi.org/10.1023/A:1009477910121

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