Deok Keun Oh
Abstract
The semiconductor industry has accepted three-dimensional integrated circuits (3D ICs) as a possible solution to address speed and power management problems. In addition, 3D ICs have recently demonstrated a huge potential in reducing wire length and increasing the density of a chip. However, the growing density in chips such as TSV-based 3D ICs has brought the increased temperature on chip and temperature gradients depending on location. Thus, through silicon via (TSV)-based 3D clock tree synthesis (CTS) causes thermal problems leading to large clock skew. We propose a novel 3D symmetrical buffered clock tree synthesis considering thermal variation. First, <u>3D</u> abstract tree topology based on <u>n</u>earest-<u>n</u>eighbor selection with <u>m</u>edian cost (3D-NNM) is constructed by pairing sinks that have similar power consumption. Second, the layer assignment of internal nodes is determined for uniform TSV distribution. Third, in thermal-aware 3D deferred merging embedding (DME), the exact location of TSV is determined and wire routing/buffer insertion are performed after the thermal profile based on grid is obtained. The proposed method is verified using a 45nm process technology and utilized a predictive technology model (PTM) with HSPICE. It is also evaluated for the IBM benchmarks and ISPD’09 benchmarks with no blockages. In experimental result, we achieve on average 19% of clock skew reduction compared to existing thermal-aware 3D CTS. Therefore, thermal-aware 3D symmetrical buffered clock tree synthesis presented in this work is very efficient for circuit reliability.
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Index Terms
- Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis
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