Tak-Yung Kim
Abstract
For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D (
- Arunachalam, V. and Burleson, W. 2008. Low-power clock distribution in a multilayer core 3d microprocessor. In Proceedings of the 18th ACM Great Lakes Symposium on VLSI. ACM, New York, 429--434. Google Scholar
Digital Library
- Banerjee, K., Souri, S., Kapur, P., and Saraswat, K. 2001. 3-D ics: A novel chip design for improving deep-submicrometer interconnect performance and system-on-chip integration. Proc. IEEE 89, 5, 602--633.Google ScholarCross Ref
- Chao, T.-H., Hsu, Y.-C., Ho, J.-M., Boese, K. D., and Kahng, A. B. 1992. Zero-skew clock routing with minimum wirelength. IEEE Trans. Circuits Syst. 39, 11, 799--814.Google ScholarCross Ref
- Chaturvedi, R. and Hu, J. 2004. Buffered clock tree for high quality ic design. In Proceedings of the 5th International Symposium on Quality Electronic Design. IEEE, Los Alamitos, CA, 381--386. Google ScholarDigital Library
- Edahiro, M. 1993. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the 30th Design Automation Conference. ACM/IEEE, 612--616. Google ScholarDigital Library
- Edahiro, M. 1994. An efficient zero-skew routing algorithm. In Proceedings of the 31st Design Automation Conference. ACM/IEEE, 375--380. Google ScholarDigital Library
- ISPD. 2009. Ispd 2009 clock network synthesis contest. http://www.sigda.org/ispd/contests/09/ispd09cts.html.Google Scholar
- ITRS. 2009. International technology roadmap for semiconductors. http://www.itrs.net/.Google Scholar
- Jackson, M. A. B., Srinnivasan, A., and Kuh, E. S. 1990. Clock routing for high-performance ics. In Proceedings of the 27th Design Automation Conference. ACM/IEEE, 573--579. Google ScholarDigital Library
- Kim, T.-Y. and Kim, T. 2010a. Bounded skew clock routing for 3d stacked ic designs: enabling trade-offs between power and clock skew. In Proceedings of the 2010 International Green Computing Conference. IEEE, Los Alamitos, CA, 525--532. Google ScholarDigital Library
- Kim, T.-Y. and Kim, T. 2010b. Clock tree embedding for 3d ics. In Proceedings of the 15th Asia and South Pacific Design Automation Conference. IEEE, Los Alamitos, CA, 486--491. Google ScholarDigital Library
- Kim, T.-Y. and Kim, T. 2010c. Clock tree synthesis with prebond testability for 3D stacked ic designs. In Proceedings of the 47th Design Automation Conference. ACM/IEEE, 723--728. Google ScholarDigital Library
- Lim, S. K. 2010. Tsv-aware 3D physical design tool needs for faster mainstream acceptance of 3D ics. http://webadmin.dac.com/knowledgecenter/2010/documents/LIM-3D_Posted.pdf. DAC.COM Knowledge Center Article.Google Scholar
- Minz, J., Zhao, X., and Lim, S. K. 2008. Buffered clock tree synthesis for 3D ics under thermal variations. In Proceedings of the 13th Asia and South Pacific Design Automation Conference. IEEE, Los Alamitos, CA, 504--509. Google ScholarDigital Library
- Mondal, M., Ricketts, A. J., Kirolos, S., Ragheb, T., Link, G., Vijaykrishnan, N., and Massoud, Y. 2007. Thermally robust clocking schemes for 3D integrated circuits. In Proceedings of the Conference on Design, Automation and Test in Europe. IEEE, Los Alamitos, CA, 1206--1211. Google ScholarDigital Library
- Pavlidis, V. F., Savidis, I., and Friedman, E. G. 2008. Clock distribution networks for 3-D integrated circuits. In Proceedings of the IEEE 2008 Custom Integrated Circuits Conference. IEEE, Los Alamitos, CA, 651--654.Google Scholar
- PTM. Predictive technology model. http://ptm.asu.edu/.Google Scholar
- Reif, R., Fan, A., Chen, K.-N., and Das, S. 2002. Fabrication technologies for three-dimensional integrated circuits. In Proceedings of the 3rd International Symposium on Quality Electronic Design. IEEE, Los Alamitos, CA, 33--37. Google ScholarDigital Library
- Restle, R. J. et al. 2001. A clock distribution network for microprocessors. IEEE J. Solid-State Circuits 36, 5, 792--799.Google ScholarCross Ref
- Takahashi, A., Inoue, K., and Kajitani, Y. 1997. Clock-tree routing realizing a clock-schedule for semisynchronous circuits. In Proceedings of the International Conference on Computer-Aided Design. ACM/IEEE, Los Alamitos, CA, 260--265. Google ScholarDigital Library
- Tezzaron. 2010. 3D ic industry summary, http://www.tezzaron.com/technology/3D_IC_Summary.html.Google Scholar
- Zhao, X., Lewis, D. L., Lee, H.-H. S., and Lim, S. K. 2009. Prebond testable low-power clock tree design for 3D stacked ics. In Proceedings of the International Conference on Computer-Aided Design. ACM/IEEE, Los Alamitos, CA, 184--190. Google ScholarDigital Library
- Zhao, X. and Lim, S. K. 2010. Power and slew-aware clock network design for through-silicon-via (tsv) based 3D ics. In Proceedings of the 15th Asia and South Pacific Design Automation Conference. IEEE, Los Alamitos, CA, 175--180. Google ScholarDigital Library
Index Terms
- Clock Tree synthesis for TSV-based 3D IC designs
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