With increasing demand for $50\text{Gb}/\mathrm{S}+$, transceivers, PAM-4 modulation has become dominant over NRZ modulation [1–5], [7], and multiphase clocking is used to maximize data rate in a given process technology. However, the use of high-resolution phase interpolators (Pls) [1] or a $2\times$ frequency oscillator (OSC) and multiple Pls [2] results in high power consumption. Therefore, baud-rate clock and data recovery (CDR) can be a great option to replace $2 \times$ oversampling CDR for the energy-efficient receiver (RX). It only requires a single phase per Ul, reducing the burden of multiphase clock generation and distribution. Recently, the Mueller-Muller (MM) phase detector (PD) has been widely utilized for baud-rate CDR in ADC-based PAM-4 RXs for elaborate equalization in a high-loss channel [3]. However, using a time-interleaved SAR ADC results in high power consumption, which is unsuitable for short-reach applications with alleviated channel loss.