In advanced technology nodes, transistors and interconnects with shrinking physical dimensions suffer large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the effect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation/aging modeling to circuit-level analysis. In addition, active techniques to counter these effects, such as clock skew tuning and voltage tuning are also covered in this paper.