André Borin Soares
ABSTRACT
Embedded consumer electronics like video processing systems require large storage capacity and high bandwidth memory access. Also, those systems are built from heterogeneous processing units, designed specifically to perform dedicated tasks in order to maximize the processing efficiency. A single off-chip memory is shared between the processing units to reduce power and save costs. The external memory access is the system bottleneck when decoding high definition video sequences in real time. A four level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The inclusion of the memory hierarchy in the system has also implications on system integration and IP reuse in a collaborative design. This work presents some issues in the integration of the memory hierarchy on the system and practical strategies used to solve them. This architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.
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Index Terms
- Integration issues on the development of an h.264/AVC video decoder SoC for SBTVD set top box
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