Ashoka Sathanur
ABSTRACT
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gated and non power-gated regions within the same block. The clustering algorithm automatically selects an optimal subset of rows that can be power-gated with a tightly controlled delay overhead. We then address the issue of interfacing different gated regions and propose a novel technique to address this issue with minimal area and power penalty. Our approach is compatible with state-of-the art logic and physical synthesis flows and it does not significantly impact design closure. We achieve leakage power reductions as high as 89% for a set of standard benchmarks, with minimum timing and area overhead.
- H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. on Electron Devices, vol. ED-32, no. 5, pp. 903--909, May 1985.Google Scholar
Cross Ref
- K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. on Electron Devices, vol. 49, pp. 2001--2007, Nov. 2002.Google ScholarCross Ref
- G. Chen and E. Friedman, "Low power repeaters driving RC interconnects with delay and bandwidth constraints," in Proc. of ASIC/SOC, pp. 335--339, 2004.Google Scholar
- H. Fatemi, S. Nazarian, and M. Pedram, "A current-based method for short circuit power calculation under noisy input waveforms," in Proc. of ASP-DAC, pp. 774--779, 2007. Google ScholarDigital Library
- Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003 edition, http://public.itrs.net/Google Scholar
- R. Rao, K. Agarwal, D. Sylvester, et al. "Approaches to runtime and standby mode leakage reduction in global buses," in Proc. of ISLPED, pp. 188--193, 2004. Google ScholarDigital Library
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A Coding framework for low-power address and data busses." IEEE Trans. on VLSI, vol. 7, no. 2, pp. 212--221, June 1998. Google ScholarDigital Library
- L. Benini, G. D. Micheli, E. Macii, et al, "Power optimization of core-based systems by address bus encoding," IEEE Trans. on VLSI, vol. 6, no. 4, pp. 551--562. Dec. 1998. Google ScholarDigital Library
- Y. Shin, S. Chae, and K. Choi, "Partial bus-invert coding for power optimization of application-specific systems," IEEE Trans. on VLSI, vol. 9, no. 2, pp. 377--383, Apr. 2001. Google ScholarDigital Library
- T. Sakurai and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. on Electron Devices, vol. 38, no. 4, pp. 887--894, Apr. 1991.Google ScholarCross Ref
- H. Zhou and D. Wong. "Global routing with crosstalk constraints," in Proc. of DAC, pp. 374--377, 1998. Google ScholarDigital Library
- I. Jiang, Y. Chang, and I. Jou, "Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing," IEEE Trans. on CAD, vol. 19, no. 9, pp. 999--1010. Sep. 2000. Google ScholarDigital Library
- R. Marculescu, D. Marculescu, and M. Pedram, "Switching activity estimation considering spatiotemporal correlations," in Proc. of ICCAD, pp. 294--299, 1994. Google ScholarDigital Library
- R. Marculescu, D. Marculescu, and M. Pedram, "Probabilistic modeling of dependencies during switching activity analysis," IEEE Trans. on CAD, vol. 17, no. 2, pp. 73--83, Feb. 1998. Google ScholarDigital Library
- M. Xakellis and F. Najm, "Statistical estimation of the switching activity in digital circuits," in Proc. of DAC, pp. 728--733, 1994. Google ScholarDigital Library
- D. Sinha, D. Khalil, Y. Ismail, and H. Zhou, "A timing dependent power estimation framework considering coupling", in Proc. ICCAD, pp. 401--407, 2006. Google ScholarDigital Library
- V. De, A. Keshavarzi, S. Narendra, et al. "Techniques for leakage power reduction," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, et al. Eds. Piscataway, NJ: IEEE, 2001.Google Scholar
- D. Lee, D. Blaauw, and D. Sylvester, "Gate oxide leakage current analysis and reduction for VLSI circuits," IEEE Trans. on VLSI, vol. 12, no. 2, pp. 155--166, Feb. 2004. Google ScholarDigital Library
- H. Veendrick, "Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE Jour. Solid-State Circuits, vol. SC-19, pp. 468--473, 1984.Google ScholarCross Ref
- K. Nose and T. Sakurai, "Analysis and future trend of short circuit power," IEEE Trans. on CAD, vol. 19, no. 9, pp. 1023--1030, Sept. 2000. Google ScholarDigital Library
- M. Pedram, "Power minimization in IC design: principles and applications," ACM Trans. on Design Automation of Electronic Systems, vol. 1, no. 1, pp. 3--56, 1996,. Google ScholarDigital Library
- E. Acar, R. Arunachalam, and S. R. Nassif, "Predicting short circuit power from timing models," in Proc. of ASP-DAC, pp. 277--282, 2003. Google ScholarDigital Library
- A. Abdollahi, F. Fallah, and M. Pedram, "An effective power mode transition technique in MTCMOS circuits," in Proc. of DAC, pp. 37--42, 2005. Google ScholarDigital Library
- Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998. Google ScholarDigital Library
- HSPICE: The Gold Standard for Accurate Circuit Simulation, www.synopsys.com/products/mixedsignal/hspice/hspice.htmlGoogle Scholar
- MOSEK Optimization Software, http://www.mosek.comGoogle Scholar
Index Terms
- Timing-driven row-based power gating
Recommendations
Optimal sleep transistor synthesis under timing and area constraints
GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSILeakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction ...
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & DesignRow-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share ...
Row-based power-gating: a novel sleep transistor insertion methodology for leakage power optimization in nanometer CMOS circuits
Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic ...
Comments