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A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

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Abstract

The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-design environments [2]. VLIW architecture allows generating optimized machine code from high-level languages exploiting Instruction Level Parallelism (ILP) [3]. Furthermore, applications requirements and time to market constraints are growing dramatically moving functionalities toward System on Chip (SoC) direction. This paper presents VLIW-SIM, an Application-Driven Architecture-design approach based on Instruction Set simulation. VLIW architectures and Instruction Set simulation were chosen to fulfill multimedia domain requirements and to implement an efficient Hw-Sw co-design environment. The VLIW-SIM simulation technology is based on pipeline status modeling, Simulation cache and Simulation Oriented Hw description. An effective support for Hw-Sw co-design requires high simulation performance (in terms of Simulated Instruction per Second—SIPS), flexibility (the ability to represent a number of different architectures) and cycle accuracy. There is a strong trade-off between these features: cycle accurate or close to cycle accurate simulation have usually low performance [4, 5]. Good simulation performance can be obtained loosing the simulator flexibility. Moreover SoC simulation requires a further degree of flexibility in simulating different components (core, co-processors, memories, buses). The proposed approach is focused on interpretative (not compiled [6]) re-configurable Instruction Set Simulator (ISS) in order to support both application design and architecture exploration. VLIW-SIM main features are: efficient host resource allocation, Instruction Set and Architecture description Flexibility (Instruction Set Dynamic Generation and Simulation Oriented Hardware Description), Step by step pipeline status tracking, Simulation Speed and Accuracy. Performance of simulation test for three validation case studies (TI TMS320C62x, TI TMS320C64x and ST200) are reported.

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References

  1. Joseph A. Fisher, “Very Long Instruction Word Architectures and the ELI-512,” in Proceedings of the 10th Annual International Symposium on Computer Architecture, Stockholm, Sweden, June 1983.

  2. F. Balarin, M. Chiodo, et al., Hardware-Software Co-Design of Embedded Systems—The POLIS Approach, Kluwer Academic Publishers, 1997.

  3. B.R. Rau, and J.A. Fisher, “Instruction Level Parallelism,” The Journal of Supercomputing, vol. 7 May 1993.

  4. K. Olukotun, M. Heinrich, and D. Ofelt, “Digital System Simulation: Methodologies and Examples,” in Proc. Design Automation Conf., June 1998, pp. 658–663.

  5. J. Rowson, “Hardware/Software Co-Simulation,” in Proc. Design Automation Conference, June 1994, pp. 439–440.

  6. C. Mills, S.C. Ahalt, and J. Fowler, “Compiled Instruction Set Simulation,” Software–Practice and Experience, vol. 21, Aug. 1991, pp. 877–889.

    Article  Google Scholar 

  7. P. Faraboschi, G. Desoli, and J.A. Fisher “The Latest Word in Digital and Media Processing,” IEEE Signal Processing Magazine, March 1998.

  8. P. Lapsley, J. Bier, A. Shoham, and E.A. Lee, “DSP Processor Fundamentals: Architectures and Features,” IEEE Press Series on Signal Processing, 1996.

  9. Berkeley Design Technology Inc, “VLIW Architectures for DSP,” DSP World/ICSPAT, Orlando Florida, November 1999.

  10. A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr, “A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language,” IEEE Transaction on Computer-Aied Design of Integrated Circuits and System, vol. 20, no. 11, 2001.

  11. R.B. Lee and M.D. Smith, “Media Processing: A New Design Target, IEEE Micro, Aug. 1996.

  12. TI, TMS320C62x/C67x CPU and Instruction Set, Reference Guide, 1998.

  13. TI, TMS320C64x Technical Overview, September 2000.

  14. P. Faraboschi, J. Fisher, G. Brown, G. Desoli, and F. Homewood, “Lx: A Technology Platform for Customizable VLIW Embedded Processing,” ISCA Vancouver, Canada, June 2000.

  15. A. Jemai, P. Kission, and A. Jerraya, “Combining Behavioral synthesis and Architectural simulation,” ASPDAC 1997.

  16. A. Jemai, P. Kission, and A.A. Jerraya, “Architectural Simulation in the Context of Behavioral Synthesis,” DATE98, Paris, France, Feb. 1998.

  17. P. Lieverse, P. Van der Wolf, E. Deprettere, and K. Vissers, “A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems,” SIPS99, IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, Oct. 1999.

  18. Eric Schnarr, Mark D. Hill, and James R. Larus, “Facile: A Language and Compiler for High-Performance Processor Simulators,” in PLDI2001, ACM SIGPLAN Conference on Programming Language Design and Implementation, Snowbird, Utah, USA, June 2001.

  19. E. Schnarr and J.R. Larus, “Fast Out-Of-Order Processor Simulation Using Memoization,” ASPLOS98, San Jose CA, Oct. 1998.

  20. J. Zhu and D.D. Gajski “An Ultra-Fast Instruction Set Simulator,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, June 2002.

  21. J.W. Ahn, S.M. Moon, aand W. Sung, “Efficient Compiled Simulation System for VLIW Code Verification,” in IEEE Annual Simulation Symposium, Boston, MA, USA, April 1998.

  22. J. Liu, M. Lajolo, and A. Sangiovanni-Vincentelli, “Software Timing Analysis Using SW/HW Cosimulation and Instruction Set Simulator,” in 6th International Workshop on Hardware/Software Codesign, Seattle, Washington, USA, March 1998.

  23. Ptolemy Home Page, http://ptolemy.eecs.berkeley.edu.

  24. L. Guerra, J. Fitzner, D. Talukdar, C. Schlaeger, B. Tabbara, and V. Zivojnovic, “Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification,” in DAC99 36th Annual Design Automation Conference, New Orleans, LA, USA, June 1999.

  25. A. Baghdadi, D. Lyonnard, N.E. Zergainoh, and A.A. Jerraya, “An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC,” DATE01 Design, Automation, and Test in Europe, Munich, Germany, March 2001.

  26. Murthy Durbhakula, Vijay S. Pai, and Sarita V. Adve, “Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors,” in HPCA99 Fifth International Symposium on High Performance Computer Architecture, Orlando, Florida, USA, Jan. 1999.

  27. Berkeley Design Technology Inc, “Choosing a DSP Processor,” White Paper 2000, http://www.bdti.com.

  28. I. Barbieri, M. Bariani, and M. Raggio, “C6XSIM: A VLIW Architecture Simulation Innovative Approach,” DCIS ‘99, Palma de Maiorca, Spain, Nov. 1999.

  29. I. Barbieri, M. Bariani, and M. Raggio, “A VLIW Architecture Simulator Innovative Approach for HW-SW Co-Design,” in ICME2000—International Conference on Multimedia and Expo 2000, New York City, July 2000.

  30. I. Barbieri, M. Bariani, and M. Raggio, “Multimedia Application Driven Instruction Set Architecture Simulation,” in ICME2002 - International Conference on Multimedia and Expo 2002, Lausanne, Aug. 2002.

  31. R.K. Gupta and G. De Micheli, “Hardware-Software Cosynthesis for Digital Systems,” IEEE Design and Test of Computers, Sep. 1993.

  32. S. Carr, “Combining Optimization for Cache and Instruction-Level Parallelism,” in Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT ‘96, Oct. 1996, pp. 238–247.

  33. Vijay S. Pai, and Sarita Adve, “Code Transformations to Improve Memory Parallelism,” The Journal of Instruction-Level Parallelism, May 2000.

  34. J. Bruns and C. Müller-Schloer, “An Integrated System-Level Modelling and Simulation Environment,” ESM ‘99 13th European Simulation Multiconference, Warsaw Poland, June 1999.

  35. AXYS Design Automation Inc, “MaxSim Developer Suite User’s Guide Version 3.0,” Document Version 1.04 September 9th, 2002.

  36. AXYS® Design Automation, Inc, http://www.axysdesign.com/.

  37. ITU-T Recommendation H.263, “Video Coding for Low Bitrate Communication,” Feb. 1998.

  38. ITU-T Recommendation G.723.1, “Dual Rate Speech Coder for Multimedia Communication Transmitting at 5.3 and 6.3 kbit/s,” March 1998.

  39. ITU-T Recommendation G.726, “40, 32,24, 16 Kbit/Sec Adaptive Differential Pulse Code Modulation (ADPCM),” Nov. 1990.

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Authors and Affiliations

  1. Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia 11 A, 16146, Genova, Italy

    Ivano Barbieri, Massimo Bariani, Alberto Cabitto & Marco Raggio

Authors
  1. Ivano Barbieri
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  2. Massimo Bariani
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  3. Alberto Cabitto
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  4. Marco Raggio
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Correspondence to Ivano Barbieri.

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Ivano Barbieri was born in Genova—Italy in 1969. He obtained its M.Sc. degree in Electronic Engineering at Genoa University—thesis on Research on Image quality evaluation alternative methods to MSE (Mean Square Error) in image coding systems for the subjective redundancy reduction—and PhD degree—thesis on Efficient methodologies for multimedia communication terminal design and testing. Since 1995 he is employed at the Department of Biophysical and Electronic Engineering (DIBE) of Genoa University. Research areas are Innovative approach on image quality evaluation, Architectural research on systems for Real time efficient implementation of video coding algorithms exploring both embedded and single-chip solutions, Real time Multimedia system (Platforms, Multiplexing and Control issues), DSP architecture and development environment, Architecture Modeling for Media processing and Embedded System for Mobile (low power) application.

Massimo Bariani was born in Genova—Italy in 1970. He obtained its M.Sc. degree in Electronic Engineering at Genoa University—thesis on development and implementation of a Multipoint Control Unit for multimedia videoconferences—and Ph.D. degree—thesis on modelling and simulation of VLIW architectures for hw-sw co-design of embedded systems. He is employed as researcher at the Department of Biophysical and Electronic Engineering (DIBE) of Genoa University. In electronic system field, his interests involve hardware design and simulation, multimedia algorithm implementation for VLIW architectures, architectural exploration, and real-time multimedia communication based on standard protocols.

Alberto Cabitto was born in Millesimo (Savona)—Italy in 1965. He was student in Electronic Engineering at Genoa University for M.Sc. degree—thesis on Compiler for Distributed Parallel computer—. Since 1994 he is consultant at the Department of Biophysical and Electronic Engineering (DIBE) of Genoa University. Since 2000 he is managing director of the SME scalab srl. His interest include programming, compilers and networking for applications and systems in the field of interactive real-time multimedia architecture.

Marco Raggio was born in Chiavari (Genova)—Italy in 1964. He obtained its M.Sc. degree in Electronic Engineering at Genoa University—thesis on development and realtime test of video compression algorithms—and Ph.D. degree—thesis on implementation and simulation of real time multimedia embedded system for videotelephony application and advanced DSP Architecture—. Since 1995 he is employed as research project manager/officer at the Department of Biophysical and Electronic Engineering (DIBE) of Genoa University. In electronic system field, his interests involve hardware design and simulation, interactive real-time multimedia architecture design i.e. for mobile terminal and surveillance systems. His activities involve also field trials setup, audit and dissemination. In networking field, he has expertise in LAN design, configuration, maintenance, security. He teach on university seminars on video coding, standards for multimedia and streaming, DSP, industrial field bus and embedded systems.

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Barbieri, I., Bariani, M., Cabitto, A. et al. A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures. J VLSI Sign Process Syst Sign Image Video Technol 41, 153–168 (2005). https://doi.org/10.1007/s11265-005-6647-2

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