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Combating I-O bottleneck using prefetching: model, algorithms, and ramifications

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Abstract

Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter (Commun. ACM 31(9):1116–1127, [1988]). More than a decade of architectural advancements have led to new features that are not captured in the I-O model—most notably the prefetching capability. We propose a relatively simple Prefetch model that incorporates data prefetching in the traditional I-O models and show how to design optimal algorithms that can attain close to peak memory bandwidth. Unlike (the inverse of) memory latency, the memory bandwidth is much closer to the processing speed, thereby, intelligent use of prefetching can considerably mitigate the I-O bottleneck. For some fundamental problems, our algorithms attain running times approaching that of the idealized random access machines under reasonable assumptions. Our work also explains more precisely the significantly superior performance of the I-O efficient algorithms in systems that support prefetching compared to ones that do not.

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Authors and Affiliations

  1. IBM India Research Lab., IBM, Plot No. 4, Block C, Institutional Area, Vasant Kunj, New Delhi, 110070, India

    Akshat Verma

  2. Department of Computer Science and Engineering, IIT Delhi, New Delhi, 1100116, India

    Sandeep Sen

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  1. Akshat Verma
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  2. Sandeep Sen
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Correspondence to Akshat Verma.

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Verma, A., Sen, S. Combating I-O bottleneck using prefetching: model, algorithms, and ramifications. J Supercomput 45, 205–235 (2008). https://doi.org/10.1007/s11227-007-0170-0

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  • DOI: https://doi.org/10.1007/s11227-007-0170-0

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