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An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

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Abstract

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.

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References

  1. Chandra A, Chakrabarty K (2002) Low-power scan testing and test data compression for system-on-a-chip. IEEE Trans Comput Aided Des Integr Circuits Syst 21(5):597–604 DOI 10.1109/43.998630

    Article  Google Scholar 

  2. Chandra A., Chakrabarty K (2002) Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. In: Proceedings of Design Automation Conference, pp 673–678

  3. Koenemann B (1991) LFSR-coded test pattern for scan designs. In: Proceedings of the European Test Conference, pp 237–242

  4. Lee J, Touba NA (2007) LFSR-reseeding scheme achieving low-power dissipation during test. Proc IEEE Trans Comput Aided Des Integr Circuits Syst 26(2):396–401

    Article  Google Scholar 

  5. Li J, Han Y, Li X (2005) Deterministic and low power BIST based on scan slicing overlapping. IEEE Int Symp Circuits Syst 6:5670–5673

    Article  Google Scholar 

  6. Rosinger PM, Al-Hashimi BM, Nicolici N (2003) Dual multiple-polynomial LFSR for low-power mixed-mode BIST. IEE Proc Comput Digit Tech 150(4):209–217 DOI 10.1049/ip-cdt:20030666

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Yonsei University, 134 Shinchon-Dong, Seodaemun-Gu, Seoul, 120-749, Korea

    Myung-Hoon Yang, Yongjoon Kim, Sunghoon Chun & Sungho Kang

Authors
  1. Myung-Hoon Yang
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  2. Yongjoon Kim
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  3. Sunghoon Chun
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  4. Sungho Kang
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Corresponding author

Correspondence to Myung-Hoon Yang.

Additional information

Responsible Editor: K. K. Saluja

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Yang, MH., Kim, Y., Chun, S. et al. An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR. J Electron Test 24, 591–595 (2008). https://doi.org/10.1007/s10836-008-5077-z

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  • DOI: https://doi.org/10.1007/s10836-008-5077-z

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