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Vacuity in practice: temporal antecedent failure

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Abstract

Different definitions of vacuity in temporal logic model checking have been suggested along the years. Examining them closely, however, reveals an interesting phenomenon. On the one hand, some of the definitions require high-complexity vacuity detection algorithms. On the other hand, studies in the literature report that not all vacuities detected in practical applications are considered a problem by the system verifier. This brings vacuity detection into an undesirable situation where the user of the model checking tool may find herself waiting a long time for results that are of no interest for her. In this paper we restrict our attention to practical usage of vacuity detection. We define Temporal Antecedent Failure, an extension of antecedent failure to temporal logic, which refines the notion of vacuity. According to our experience, this type of vacuity always indicates a problem in the model, environment or property. We show how vacuity information can be derived from the automaton built for the original property, and we introduce the notion of vacuity explanation. Our experiments demonstrate that this type of vacuity as well as its reasons can be computed with a negligible increase in the overall runtime.

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References

  1. Aho AV, Sethi R, Ullman JD (1986) Compilers: princiles, techniques, and tools. Addison-Wesley, Boston

    Google Scholar 

  2. Armoni R, Fix L, Flaisher A, Grumberg O, Piterman N, Tiemeyer A, Vardi MY (2003) Enhanced vacuity detection in linear temporal logic. In: Proceedings of the 15th international conference on computer aided verification (CAV), Boulder, CO, USA, 8–12 July 2003, pp 368–380

  3. Baumgartner J, Mony H, Paruthi V, Kanzelman R, Janssen G (2006) Scalable sequential equivalence checking across arbitrary design transformations. In: 24th International Conference on Computer Design (ICCD), San Jose, CA, USA, 1–4 Oct 2006, pp. 259–266

  4. Beatty DL, Bryant RE (1994) Formally verifying a microprocessor using a simulation methodology. In: 31st Design automation conference (DAC), San Diego, CA, USA, 6–10 June 1994, pp 596–602

  5. Beer I, Ben-David S, Eisner C, Rodeh Y (1997) Efficient detection of vacuity in ACTL formulas. In: Proceedings of the 9th international conference on computer aided verification (CAV), Haifa, Israel, 22-25 June 1997, pp 279–290

  6. Beer I, Ben-David S, Eisner C, Rodeh Y (2001) Efficient detection of vacuity in temporal model checking. Form Methods Syst Des 18(2):141–163

    Article  MATH  Google Scholar 

  7. Beer I, Ben-David S, Landver A (1998) On-the-fly model checking of RCTL formulas. In: Proceedings of the 10th international conference on computer aided verification (CAV), Vancouver, BC, Canada, 28 June–2 1998, pp 184–194

  8. Ben-David S, Fisman D, Ruah S (2004) Automata construction for regular expressions in model checking, June. IBM research report H-0229

  9. Ben-David S, Fisman D, Ruah S (2005) The safety simple subset. In: Hardware and software verification and testing, First international Haifa verification conference (HVC). Haifa, Israel, 13–16 Nov 2005, Revised Selected Papers, pp 14–29

  10. Berry G, Sethi R (1986) From regular expression to deterministic automata. Theo Comput Sci 48:117–126

    Article  MATH  MathSciNet  Google Scholar 

  11. Biere A, Cimatti A, Clarke EM, Zhu Y (1999) Symbolic model checking without BDDs. In: Tools and algorithms for construction and analysis of systems, 5th international conference (TACAS), held as part of the European joint conferences on the theory and practice of software (ETAPS), Amsterdam, The Netherlands, 22–28 March 1999, pp 193–207

  12. Bjesse P, Claessen K (2000) Sat-based verification without state space traversal. In: 3rd international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 1-3 Nov 2000, pp 372–389

  13. Boule M, Zilic Z (2007) Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation. In: Proceedings of the 12th conference on Asia South Pacific design automation (ASP-DAC), Yokohama, Japan, 23-26 Jan 2007, pp 324–329

  14. Bradley AR (2011) Sat-based model checking without unrolling. In: Proceedings of the 12th international conference on verification, model checking, and abstract interpretation (VMCAI), Austin, TX, USA, 23-25 Jan 2011, pp 70–87

  15. Bryant RE, Chauhan P, Clarke EM, Goel A (2000) A theory of consistency for modular synchronous systems. In: Proceedings of the 3rd international conference on formal methods in computer-aided design, Austin, Texas, USA, 1–3 Nov 2000, pp 486–504

  16. Bustan D, Fisman D, Havlicek J (2005) Automata construction for PSL. Technical Report MCS05-04, The Weizmann Institute of Science, May 2005

  17. Bustan D, Flaisher A, Grumberg O, Kupferman O, Vardi Y (2005) Regular vacuity. In: Proceedings of the 13th IFIP WG 10.5 Advanced Research Working Conference on correct hardware design and verification methods (CHARME’05), Saarbriiucken, Germany, 3–6 Oct 2005, pp 191–206

  18. Cerny E, Dudani S, Havlicek J, Korchemny D (2010) The power of assertions in SystemVerilog. Springer, London

    Book  Google Scholar 

  19. Chechik M, Gheorghiu M, Gurfinkel A (2007) Finding environment guarantees. In: Proceedings of the 10th international conference on fundamental approaches to software engineering (FASE), held as part of the joint European conferences on theory and practice of software (ETAPS), Braga, Portugal, 24 March-1 April 2007, pp 352–367

  20. Chockler H, Gurfinkel A, Strichman O (2008) Beyond vacuity: towards the strongest passing formula. In: Formal methods in computer-aided design (FMCAD), Portland, Oregon, USA, 17-20 Nov 2008, pp 1–8

  21. Chockler H, Kupferman O, Vardi MY (2006) Coverage metrics for formal verification. STTT 8(4–5):373–386

    Article  Google Scholar 

  22. Chockler H, Kupferman O, Vardi MY (2006) Coverage metrics for temporal logic model checking. Form Methods Syst Des 28(3):189–212

    Article  MATH  Google Scholar 

  23. Chockler H, Strichman O (2007) Easier and more informative vacuity checks. In: 5th ACM & IEEE international conference on formal methods and models for co-design (MEMOCODE), Nice, France, 30 May-1 June, pp 189–198

  24. Chockler H, Strichman O (2009) Before and after vacuity. Form Methods Syst Des 34(1):37–58

    Article  MATH  Google Scholar 

  25. Clarke EM, Emerson EA (1981) Design and synthesis of synchronization skeletons using branchingtime temporal logic. In Proceedings of the workshop on logics of programs,Yorktown Heights, New York, May 1981, pp 52–71

  26. Clarke EM, Grumberg O, Peled D (2000) Model checking. The MIT Press, Cambridge

    Google Scholar 

  27. Dong Y, Saran-Starosta B, Ramakrishnan CR, Smolka SA (2002) Vacuity checking in the modal Mu-claculus. In: Proceeding of the 9th international conference on algebraic methodology and software technology (AMAST), Saint-Gilles-les-Bains, Reunion Island, France, 9-13 Sept 2002, pp 147–162

  28. Eisner C, Fisman D (2006) A practical introduction to PSL. Springer, Berlin

    Google Scholar 

  29. Fisman D, Kupferman O, Sheinvald-Faragy S, Vardi MY (2008) A framework for inherent vacuity. In: Proceedings of the 4th International haifa verification conference (HVC) on hardware and software: verification and testing, Haifa, Israel, 27–30 Oct 2008, pp 7–22

  30. Glushkov VM (1953) The abstract theory of automata. Russ Math Surv 16:1–53

    Article  Google Scholar 

  31. Große D, Wille R, Kühne U, Drechsler R (2009) Contradictory antecedent debugging in bounded model checking. In: Proceedings of the 19th ACM great lakes symposium on VLSI, Boston Area, MA, USA, 10–12 May 2009, pp 173–176

  32. Gurfinkel A, Chechik M (2004) Extending extended vacuity. In: Proceedings of the 5th international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 15–17 Nov 2004, pp 306–321

  33. Gurfinkel A, Chechik M (2004) How vacuous is vacuous? In: Proceedings of the 10th international conference on tools and algorithms for the construction and analysis of systems (TACAS), held as part of the joint European conferences on theory and practice of software (ETAPS), Barcelona, Spain, 29 March-2 April 2004, pp 451–466

  34. Hopcroft JE, Ullman JD (1979) Introduction to automata theory, languages, and computation. Addison-Wesley Series in Computer Science. Addison-Wesley, Boston

  35. IEEE Standard for Property Specification Language (PSL), Annex B. IEEE Std 1850™-2010

  36. IEEE Standard for SystemVerilog—unified hardware design, specification, and verification language, Annex F. IEEE Std 1800™-2009

  37. Kupferman O (2006) Sanity checks in formal verification. In: Proceedings of the 17th International conference on concurrency theory (CONCUR), Bonn, Germany, Aug 27–30, 2006, pp 37–51

  38. Kupferman O, Li W, Seshia SA (2008) A theory of mutations with applications to vacuity, coverage, and fault tolerance. In: Formal methods in computer-aided design (FMCAD), Portland, Oregon, USA, 17–20 Nov 2008, pp 1–9

  39. Kupferman O, Lustig Y (2007) Lattice automata. In: Proceedings of the 8th International Conference on verification, model Checking, and abstract interpretation (VMCAI), Nice, France, 14–16 Jan 2007, pp 199–213

  40. Kupferman O, Vardi MY (1999) Vacuity detection in temporal model checking. In: Conference on correct hardware design and verification methods, pp 82–96

  41. Kupferman O, Vardi MY (2003) Vacuity detection in temporal model checking. Softw tools technol trans 4(2):224–233

    Article  Google Scholar 

  42. Maidl M (2000) The common fragment of CTL and LTL. In: 41st annual symposium on foundations of computer science (FOCS), Redondo Beach, California, USA, 12–14 Nov 2000, pp 643–652

  43. McNaughton R, Yamada H (1960) Regular expressions and state graphs for automata. IEEE Trans Electron Comput EC–9(1):38–47

    Google Scholar 

  44. Mony H, Baumgartner J, Mishchenko A, Brayton RK (2009) Speculative reduction-based scalable redundancy identification. In: Design, automation and test in Europe (DATE), Nice, France, 20–24 April 2009, pp 1674–1679

  45. Mony H, Baumgartner J, Paruthi V, Kanzelman R (2005) Exploiting suspected redundancy without proving it. In: Proceedings of the 42nd design automation conference (DAC), San Diego, CA, USA, 13–17 June 2005, pp 463–466

  46. Mony H, Baumgartner J, Paruthi V, Kanzelman R, Kuehlmann A (2004) Scalable automated verification via expert-system guided transformations. In: Proceedings of the 5th international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 15–17 Nov 2004, pp 159–173

  47. Namjoshi KS (2001) Certifying model checkers. In: Proceedings of the 13th international conference on computer aided verification (CAV), Paris, France, 18-22 July 2001, pp 2–13

  48. Namjoshi KS (2004) An efficiently checkable, proof-based formulation of vacuity in model checking. In: Proceedings of the 16th international conference on computer aided verification (CAV), Boston, MA, USA, 13-17 July 2004, pp 57–69

  49. Peled D, Pnueli A, Zuck LD (2001) From falsification to verification. In FSTTCS: Proceedings of the 21st conference on foundations of software technology and theoretical computer Science, Bangalore, India, 13-15 Dec 2001, pp 292–304

  50. Pnueli A (1977) The temporal logic of programs. In: 18th annual symposium on foundations of computer science, Providence, Rhode Island, USA, 31 Oct - 1 Nov 1977, pp 46–57

  51. Purandare M, Somenzi F (2002) Vacuum cleaning CTL formulae. In: Proceedings of the 14th international conference on computer aided verification (CAV), Copenhagen, Denmark, 27-31 July 2002, pp 485–499

  52. Purandare M, Wahl T, Kroening D (2009) Strengthening properties using abstraction refinement. In: Design, automation and test in Europe (DATE), Nice, France, 20-24 April 2009, pp 1692–1697

  53. Quielle J, Sifakis J (1982) Specification and verification of concurrent systems in CESAR. In: Proceedings of the 5th colloquium international symposium on programming, Torino, Italy, 6-8 April 1982, pp 337–351

  54. Samer M, Veith H (2004) Parameterized vacuity. In: Proceedings of the 5th international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 15-17 Nov 2004, pp 322–336

  55. Samer M, Veith H (2007) On the notion of vacuous truth. In: Proceedings of the 14th international conference on logic for programming, articial intelligence, and reasoning (LPAR), Yerevan, Armenia, 15-19 Oct 2007, pp 2–14

  56. Sheeran M, Singh S, Stålmarck G (2000) Checking safety properties using induction and a sat-solver. In: Proceedings of the 3rd international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 1-3 Nov 2000, pp108–125

  57. Simmonds J, Davies J, Gurfinkel A, Chechik M (2007) Exploiting resolution proofs to speed up LTL vacuity detection for BMC. In: Proceedings of the 7th international conference on formal methods in computer-aided design (FMCAD), Austin, Texas, USA, 11-14 Nov 2007, pp 3–12

  58. Winkelmann K, Trylus H-J, Stoffel D, Fey G (2004) Cost-efficient block verification for a UMTS uplink chip-rate coprocessor. In: Design, automation and test in Europe conference and exposition (DATE), Paris, France, 16-20 Feb 2004, pp 162–167

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Correspondence to Shoham Ben-David.

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Shoham Ben-David is grateful to the Azrieli Foundation for the award of an Azrieli Fellowship.

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Ben-David, S., Copty, F., Fisman, D. et al. Vacuity in practice: temporal antecedent failure. Form Methods Syst Des 46, 81–104 (2015). https://doi.org/10.1007/s10703-014-0221-0

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