Abstract
Previous works for full-chip leakage power estimation are all based on Wilkinson’s approach which approximates sum of lognormal random variables as another lognormal by matching the first and second moments. In this paper we will show that natural logarithm of leakage deviates from normal distribution by scaling transistor sizes, as a result distribution of leakage power cannot be described by lognormal distribution anymore. We will introduce generalized extreme value distribution as the best candidate for full-chip leakage power estimation and we will prove its superiority over lognormal approximation through simulation results in 45nm technology.
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Khosropour, A., Aghababa, H., Afzali-Kusha, A., Forouzandeh, B. (2011). Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution. In: Ayala, J.L., GarcĂa-Cámara, B., Prieto, M., Ruggiero, M., Sicard, G. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. PATMOS 2011. Lecture Notes in Computer Science, vol 6951. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24154-3_18
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DOI: https://doi.org/10.1007/978-3-642-24154-3_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24153-6
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